发明授权
US4954992A Random access memory having separate read out and write in bus lines for
reduced access time and operating method therefor
失效
具有单独的读出和写入总线的随机存取存储器,以减少访问时间及其操作方法
- 专利标题: Random access memory having separate read out and write in bus lines for reduced access time and operating method therefor
- 专利标题(中): 具有单独的读出和写入总线的随机存取存储器,以减少访问时间及其操作方法
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申请号: US269757申请日: 1988-11-08
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公开(公告)号: US4954992A公开(公告)日: 1990-09-04
- 发明人: Masaki Kumanoya , Hirofumi Shinohara , Katsumi Dosaka , Yasuhiro Konishi , Takahiro Komatsu , Hiroyuki Yamasaki
- 申请人: Masaki Kumanoya , Hirofumi Shinohara , Katsumi Dosaka , Yasuhiro Konishi , Takahiro Komatsu , Hiroyuki Yamasaki
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX62-327940 19871224; JPX63-11257 19880120; JPX63-24284 19880203
- 主分类号: G11C7/06
- IPC分类号: G11C7/06 ; G11C7/10 ; G11C11/4091 ; G11C11/4096
摘要:
A dynamic random access memory device includes a pair of write-in data transferring buses for transferring data to be written, a pair of read-out data transferring buses for transferring data to be read provided additionally and separately from the write-in data transferring bus pair and a plurality of current mirror type sense amplifiers formed of CMOS transistors and each amplifier being provided between a bit line pair and the read-out data transferring bus pair and having input nodes connected to the corresponding bit line pair and the read-out data transferring bus pair forming output nodes thereof. The current mirror type sense amplifiers of CMOS transistors are activated in response to an output of a column decoder at earlier time than the time when conventional flip-flop type sense amplifiers are activated.
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