A fully differential sigma-delta signal processor for use in high-speed voiceband or higher-frequency applications. The processor receives the two polarities of a differential input signal and passes them to a differential-amplifier integrator through a switched sampling capacitor arrangement. The capacitors are each alternately and concurrently switched back and forth between the two signal paths for the two polarities of the input signal responsive to a clock signal in such a manner as to sample and integrate the input signal at an effective signal transfer rate of at least twice the clock frequency. An analog-to-digital converter defines a digital feedback-control signal characteristic of the integrator output signal. A second switched-capacitor arrangement selectively applies a feedback signal to the integrator inputs, responsive to the digital control signal, at a switching rate comparable to the effective signal transfer rate through the integrator.