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公开(公告)号：US4794349A
公开(公告)日：1988-12-27
申请号：US82608
申请日：1987-08-07
IPC分类号： H01L27/092 , H01L21/8238 , H03F1/08 , H03F3/20 , H03F3/26 , H03F3/30 , H03F3/34 , H03F3/45 , H03F3/68
CPC分类号： H03F3/3064 , H03F1/086 , H03F3/3028 , H03F3/45192 , H03F3/4565 , H03F2203/45421 , H03F2203/45574 , H03F2203/45674
摘要： A fully differential, CMOS, operational power amplifier, particularly useful as output buffer in monolithic analog subsystems, includes an input differential stage, two gain stages and two output stages. Each output stage may be individually provided with a functional feedback loop and locally compensated for reestablishing sufficient stability. An output common mode control circuit, operable in a continuous or sampled manner, is also contemplated, as well as a special circuit for controlling the DC biasing current through the output stages under rest conditions. The amplifier may be used indifferently as a balanced (differential) output or as a single-ended output amplifier without any depression of its performances.
摘要翻译： 全差分CMOS运算功率放大器，特别适用于单片模拟子系统中的输出缓冲器，包括输入差分级，两个增益级和两个输出级。 每个输出级可以单独地设置有功能反馈回路，并且被局部补偿以重新建立足够的稳定性。 也可考虑以连续或采样方式操作的输出共模控制电路，以及用于在静止条件下控制通过输出级的直流偏置电流的特殊电路。 放大器可以无差别地用作平衡（差分）输出或单端输出放大器，而不会降低其性能。
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2.发明授权
公开(公告)号：US4633425A
公开(公告)日：1986-12-30
申请号：US738281
申请日：1985-05-28
申请人： Daniel Senderowicz
发明人： Daniel Senderowicz
CPC分类号： H03F3/45479 , H03F3/005 , H03H19/004 , H03F2200/372
摘要： An integrated circuit for filtering signals by having cascaded switched capacitor sampling filters. The circuit includes a transmit section which has an anti-aliasing filter, a core section filter, a highpass filter and an encoder for providing analog-to-digital conversion. Each successive filter is sampled at a lower rate to inhibit anti-aliasing. The circuit also includes a receive section which has a digital-to-analog decoder, an output buffer, a receiver core filter and a power amplifier.
摘要翻译： 用于通过级联开关电容器采样滤波器对信号进行滤波的集成电路。 该电路包括具有抗混叠滤波器，芯部滤波器，高通滤波器和用于提供模数转换的编码器的发射部分。 以较低的速率对每个连续的滤波器进行采样以抑制抗混叠。 电路还包括具有数模转换解码器，输出缓冲器，接收器芯滤波器和功率放大器的接收部分。
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公开(公告)号：US4920510A
公开(公告)日：1990-04-24
申请号：US63258
申请日：1987-06-17
CPC分类号： H03H17/02
摘要： The sampled-data band-pass filter device is based on the phenomemon of aliasing, and allows the substantially unattenuated passage of the components of an input signal at a frequency included within an interval comprised between a first frequency (f.sub.sL) and a second frequency (f.sub.sH), arranged around a third frequency (f.sub.sO), while it substantially attenuates the components of the input signal at frequencies outside said interval, and furthermore automatically performs the shift to low-frequency, around a fourth frequency (f.sub.O), of the components of the input signal which have passed without attenuation. According to the invention, the device comprises, as filter element, a sampled-data band-pass filter which employs, as sampling frequency, a fifth frequency (f.sub.s) equal to a whole submultiple of a sixth frequency (nf.sub.s) equal to the sum of the third frequency (f.sub.sO) and the fourth frequency (f.sub.O), having, as lower and upper cutoff frequencies, respectively the difference between the sixth frequency and the second frequency (nf.sub.s -f.sub.sH) and the difference between the sixth frequency and the first frequency (nf.sub.s -f.sub.sL).
摘要翻译： 采样数据带通滤波器装置基于混叠的特征，并且允许以包括在第一频率（fsL）和第二频率（fsL）之间的间隔内的频率的输入信号的分量的基本上未衰减的通过 fsH），其大致在第三频率（fs0）周围的频率衰减输入信号的分量，并且还自动地执行向组件的第四频率（f0）附近的低频移位 通过没有衰减的输入信号。 根据本发明，该装置包括作为滤波器元件的采样数据带通滤波器，采样数据带通滤波器采用等于等于总和的第六频率（nfs）的整数倍的第五频率（fs）作为采样频率 具有分别为第六频率和第二频率（nfs-fsH）之间的差和第六频率与第一频率之间的差的第三频率（fs0）和第四频率（f0）分别为下限和上限截止频率 频率（nfs-fsL）。
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4.发明授权Method and apparatus for pulse code modulation combination chip having an improved autozero circuit 失效具有改进的自动调零电路的脉冲编码调制组合芯片的方法和装置
公开(公告)号：US4805192A
公开(公告)日：1989-02-14
申请号：US936369
申请日：1986-12-01
CPC分类号： H03M1/0607 , H03M1/825
摘要： In a Pulse Code Modulated (PCM) circuit chip, apparatus in the transmit path to compensate for an offset voltage signal from a band-pass filter includes an up-down counter which is actuated to provide a digital value equivalent to the offset signal and a digital to analog converter coupled to the counter to provide an analog signal representing the digital value in the counter. During an initialization phase, the counter is incremented until the digital value of the counter provides, by means of the digital to analog converter, an analog signal that compensates for the off-set signal. After the initialization phase when the band-pass filter's offset voltage is compensated, then other circuitry including an exclusive OR gate and an associated overflow counter are used to eneable or disable the up-down counter to insure that the PCM output signal is an accurate representation of the analog input signal. The up-down counter, during the operation phase following the initialization phase, is only enabled when the analog input signal is not present.
摘要翻译： 在脉冲编码调制（PCM）电路芯片中，用于补偿来自带通滤波器的偏移电压信号的传输路径中的装置包括被启动以提供与偏移信号等效的数字值的升降计数器，以及 数模转换器耦合到计数器以提供表示计数器中的数字值的模拟信号。 在初始化阶段期间，计数器递增，直到计数器的数字值通过数模转换器提供补偿偏移信号的模拟信号。 在对带通滤波器的偏移电压进行补偿的初始化阶段之后，使用包括异或门和相关联的溢出计数器的其它电路来使能或禁止升降计数器，以确保PCM输出信号是准确的表示 的模拟输入信号。 在初始化阶段之后的运行阶段，只有当模拟输入信号不存在时，才能使能上拉计数器。
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5.发明授权Highly selective passive filters using low-Q planar capacitors and inductors 有权使用低Q平面电容器和电感器的高选择性无源滤波器公开(公告)号：US08058950B1
公开(公告)日：2011-11-15
申请号：US12082922
申请日：2008-04-14
申请人： Daniel Senderowicz
发明人： Daniel Senderowicz
IPC分类号： H03H7/01
CPC分类号： H03H7/09 , H03H5/02 , H03H7/1775
摘要： A highly selective frequency filter is created from lossy components such as found in standard integrated circuit technologies, including particularly CMOS technologies, without the use of active loss cancellation circuitry. The filter configuration is based on using inductively coupled planar inductors for introducing a mutual inductance factor that advantageously alters the frequency response of the filter.
摘要翻译： 高选择性频率滤波器由有损组件产生，例如在标准集成电路技术（包括特别是CMOS技术）中找到的，而不使用有源损耗消除电路。 滤波器配置基于使用电感耦合平面电感器来引入有利地改变滤波器的频率响应的互感因子。
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公开(公告)号：US06697444B1
公开(公告)日：2004-02-24
申请号：US09499631
申请日：2000-02-08
IPC分类号： H04D100
CPC分类号： G06F17/15
摘要： An analog input signal that is sampled at a predetermined rate is multiplied by a corresponding binary code sequence, i.e. “+1” or “−1” by the multiplier. The output of this multiplier is applied in conjunction with a signal supplied by the negative feed back circuit to the analog integrator. The quantization circuit quantizes the output signal of the analog integrator into N levels and outputs a digital word. This digital word is delayed by a unit time interval by a digital delay circuit and then processed by the above mentioned negative feed back circuit. As a result of this signal magnitude reducing process, the required integrating capacitance can be minimized without risks of saturation effects. Additionally, the output is already in digital form as required by the subsequent system blocks.
摘要翻译： 以预定速率采样的模拟输入信号乘以相应的二进制码序列，即乘法器为“+1”或“-1”。 该乘法器的输出结合由负反馈电路提供给模拟积分器的信号。 量化电路将模拟积分器的输出信号量化为N个电平并输出数字字。 该数字字由数字延迟电路延迟单位时间间隔，然后由上述负反馈电路处理。 作为该信号幅度降低处理的结果，可以最小化所需的积分电容，而不会产生饱和效应的风险。 此外，输出已经是随后系统块所要求的数字形式。
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公开(公告)号：US5099239A
公开(公告)日：1992-03-24
申请号：US410566
申请日：1989-09-21
CPC分类号： H03M1/12 , H01L27/0805 , H03M1/468 , H03M1/804
摘要： A multichannel ADC is fabricated on a single IC with each analog channel for concurrently processing input analogue signal in a pipelined manner and including a dual purpose intermediate amplifier for amplifying an input voltage to be converted and providing a reference voltage for use during conversion. A unique capacitor array reduces the area required to implement the convertors.
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公开(公告)号：US5140327A
公开(公告)日：1992-08-18
申请号：US678495
申请日：1991-04-01
CPC分类号： H03M1/12 , H01L27/0805 , H03M1/468 , H03M1/804
摘要： An improved MOS capacitor array formed on a semiconductor substrate comprises rectangular strips of an active region overlapped by rectangular strips of conductive material. The active region and conductive material are separated by an insulating layer. The strips form an array of capacitors which are more tightly packed than the prior art and which are less sensitive to alignment errors than the prior art.
摘要翻译： 形成在半导体衬底上的改进的MOS电容器阵列包括由导电材料的矩形条带重叠的有源区的矩形条。 有源区和导电材料被绝缘层隔开。 条带形成电容器阵列，其比现有技术更紧密地包装，并且对比对误差比现有技术更不敏感。
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9.发明授权Method of reconstructing an analog signal, particularly in digital telephony applications, and a circuit device implementing the method 失效重建模拟信号的方法，特别是数字电话应用中的模拟信号，以及实现该方法的电路装置
公开(公告)号：US5014304A
公开(公告)日：1991-05-07
申请号：US469759
申请日：1990-01-24
IPC分类号： H04B14/04
CPC分类号： H04B14/04
摘要： A method of reconstructing an analog signal, particularly for digital telephony, comprises a first step of digital-to-analog conversion, wherein a first reconstruction of the analog signal is provided by introducing a distortion component into the frequency spectrum whose amplitude decreases with the signal frequency, and a second step of filtering carried out by means of a reconstruction filter provided with integrators and having a cut-off frequency F.sub.t. That attenuating distortion component is utilized instead of one of the integrators in the reconstruction filter, to afford a reduction of the overall design of the circuit device operating in accordance with this method, and bring about, as a result, decreased occupation of the integrated circuit and power dissipation.
摘要翻译： 一种重建模拟信号，特别是数字电话的方法包括数模转换的第一步骤，其中模拟信号的第一重建是通过将失真分量引入振幅随信号幅度减小的频谱中而提供的 频率，以及通过具有积分器并具有截止频率Ft的重构滤波器进行滤波的第二步骤。 利用该衰减失真分量代替重构滤波器中的一个积分器，以减少根据该方法工作的电路装置的总体设计，并且导致集成电路的占用减少 和功耗。
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公开(公告)号：US5001725A
公开(公告)日：1991-03-19
申请号：US354654
申请日：1989-05-19
申请人： Daniel Senderowicz , Nan-Sheng Lin
发明人： Daniel Senderowicz , Nan-Sheng Lin
IPC分类号： H03M3/02
CPC分类号： H04L25/0274 , H03M3/34 , H03M3/43 , H03M3/454
摘要： A fully differential sigma-delta signal processor for use in high-speed voiceband or higher-frequency applications. The processor receives the two polarities of a differential input signal and passes them to a differential-amplifier integrator through a switched sampling capacitor arrangement. The capacitors are each alternately and concurrently switched back and forth between the two signal paths for the two polarities of the input signal responsive to a clock signal in such a manner as to sample and integrate the input signal at an effective signal transfer rate of at least twice the clock frequency. An analog-to-digital converter defines a digital feedback-control signal characteristic of the integrator output signal. A second switched-capacitor arrangement selectively applies a feedback signal to the integrator inputs, responsive to the digital control signal, at a switching rate comparable to the effective signal transfer rate through the integrator.
摘要翻译： 用于高速语音频段或更高频率应用的全差分Σ-Δ信号处理器。 处理器接收差分输入信号的两个极性，并通过开关采样电容器布置将它们传递到差分放大器积分器。 这些电容器在输入信号的两个极性的两个信号路径之间来回交替并且并发地响应于时钟信号，以便以至少的有效信号传送速率对输入信号进行采样和积分 两倍于时钟频率。 模数转换器定义积分器输出信号的数字反馈控制信号特性。 响应于数字控制信号，第二开关电容器组合以与通过积分器的有效信号传输速率相当的开关速率选择性地将积分器输入的反馈信号施加到积分器输入端。
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