发明授权
US5006477A Method of making a latch up free, high voltage, CMOS bulk process for
sub-half micron devices
失效
为半微米器件制造无闩锁高压CMOS体积工艺的方法
- 专利标题： Method of making a latch up free, high voltage, CMOS bulk process for sub-half micron devices
- 专利标题（中）： 为半微米器件制造无闩锁高压CMOS体积工艺的方法
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申请号： US275833申请日： 1988-11-25
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公开(公告)号： US5006477A公开(公告)日： 1991-04-09
- 发明人: Joseph E. Farb
- 申请人： Joseph E. Farb
- 申请人地址： CA Los Angeles
- 专利权人： Hughes Aircraft Company
- 当前专利权人： Hughes Aircraft Company
- 当前专利权人地址： CA Los Angeles
- 主分类号： H01L21/265
- IPC分类号： H01L21/265 ; H01L21/336 ; H01L21/8238 ; H01L27/08 ; H01L27/092 ; H01L29/78
摘要：
A process for forming MOS devices having graded source and drain regions. The source and drain regions are lightly doped by ion implantation and then subjected to thermal cycling to diffuse the implanted impurities. The source and drain regions are then heavily doped to form source and drain regions having a heavily doped subregion and a lightly doped subregion. Devices made pursuant to the process, which can be made less than one-half micron, are not subject to gate oxide charging and have high snapback voltages.
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