公开(公告)号：US4837051A

公开(公告)日：1989-06-06

申请号：US222308

申请日：1988-07-21

申请人： Joseph E. Farb ,  Maw R. Chin

发明人： Joseph E. Farb ,  Maw R. Chin

IPC分类号： H01L21/768

CPC分类号： H01L21/76879

摘要： A process is disclosed for filling contact or via openings in an integrated circuit with electrically conductive plugs. The process includes the steps of (a) forming one or more openings in an planarized oxide layer, where the one or more openings is disposed over and exposes semi-insulating or conductive regions, and (b) filling the one or more openings with conductive material to substantially the same level as the adjacent surfaces of the oxide layer to form respective planarized conductive plugs.A further aspect of the invention is directed to a process which includes the steps of (a) forming first one or more openings of a first predetermined depth in a planarized oxide layer, the first one or more openings being disposed over the exposing respectively associated semi-insulating or conductive regions; (b) partially filling the first one or more openings with conductive material to a level corresponding to a second predetermined depth; (c) forming second one or more openings of the second predetermined depth in the planarized oxide layer, the second one or more openings being disposed over the exposing respectively associated semi-insulating or conductive regions; and (d) filling the first and second one or more openings to substantially the same level to form respective planarized plugs in the opeinings.

摘要翻译： 公开了一种用于在具有导电塞的集成电路中填充接触或通孔的方法。 该方法包括以下步骤：（a）在平坦化氧化物层中形成一个或多个开口，其中所述一个或多个开口设置在半绝缘或导电区域上，并且暴露出半绝缘或导电区域，以及（b）用一个或多个开口填充导电 材料与氧化物层的相邻表面基本相同的水平，以形成相应的平坦化的导电塞。 本发明的另一方面涉及一种方法，其包括以下步骤：（a）在平坦化的氧化物层中形成第一预定深度的第一个或多个开口，所述第一个一个或多个开口设置在所述暴露分别相关联的半 绝缘或导电区域; （b）用导电材料将第一个或多个开口部分地填充到与第二预定深度相对应的水平; （c）在所述平坦化氧化物层中形成所述第二预定深度的第二一个或多个开口，所述第二一个或多个开口设置在所述暴露分别相关的半绝缘或导电区域上; 和（d）将第一和第二一个或多个开口填充到基本上相同的水平面以在操作中形成相应的平面化塞子。

公开(公告)号：US5006477A

公开(公告)日：1991-04-09

申请号：US275833

申请日：1988-11-25

申请人： Joseph E. Farb

发明人： Joseph E. Farb

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/823814 ,  H01L29/78 ,  Y10S148/053

摘要： A process for forming MOS devices having graded source and drain regions. The source and drain regions are lightly doped by ion implantation and then subjected to thermal cycling to diffuse the implanted impurities. The source and drain regions are then heavily doped to form source and drain regions having a heavily doped subregion and a lightly doped subregion. Devices made pursuant to the process, which can be made less than one-half micron, are not subject to gate oxide charging and have high snapback voltages.

摘要翻译： 一种用于形成具有分级源极和漏极区域的MOS器件的工艺。 源极和漏极区域通过离子注入轻掺杂，然后进行热循环以扩散植入的杂质。 然后，源极和漏极区域被重掺杂以形成具有重掺杂子区域和轻掺杂子区域的源区和漏区。 根据该方法制造的器件可以制成小于半微米，不经过栅极氧化物充电并具有高的回跳电压。

公开(公告)号：US5528067A

公开(公告)日：1996-06-18

申请号：US438132

申请日：1995-05-08

申请人： Joseph E. Farb

发明人： Joseph E. Farb

IPC分类号： G01R33/07 ,  H01L29/82 ,  H01L43/00

CPC分类号： G01R33/07 ,  Y10S73/02

摘要： A solid state triode employs the Hall effect to asymmetrically proportion flow of current through different branches of a number of cascaded bifurcated N- charge carrier channels (10,18,20), thereby providing an indication of strength and direction of an applied magnetic field by measuring magnitude and sense of the difference between currents flowing in the two channel branches (14,16,24,26,30,32). The solid state triode is formed on an silicon-on-insulator (SOI) substrate (47,48,49) in which an N+ source region (54) and at least two end N+ drain regions (56,58) are interconnected by an N- charge carrier channel (60) that is defined by a plurality of P+ regions (64a,64b,64c,64d) in a thin single crystal silicon substrate (49) between the source and drain regions (54,56,58). A polysilicon gate (52) overlies the N- channel and acts as a self-aligning mask during manufacture of the triode to precisely align the N+ and P+ doping to the polysilicon gate configuration. The SOI has a very thin N- doped layer to which the N+ and P+ doping is applied in steps of successively different energy levels so that the doping extends completely through the N- layer and is uniform throughout the thickness of the layer. The N- channel is narrow and has a width at least twice the thickness of the crystal silicon uppermost layer of the SOI substrate.

摘要翻译： 固态三极管采用霍尔效应使不对称比例的电流流过多个级联分叉的N-电荷载流子通道（10,18,20）的不同分支，由此提供施加磁场强度和方向的指示， 测量在两个通道分支（14,16,24,26,30,32）中流动的电流之间的差异的大小和感觉。 固体三极管形成在绝缘体上硅（SOI）衬底（47,48,49）上，其中N +源极区（54）和至少两个末端N +漏极区（56,58）通过 在源极和漏极区域之间的薄单晶硅衬底（49）中由多个P +区域（64a，64b，64c，64d）限定的N-电荷载流子通道（60）。 多晶硅栅极（52）覆盖N沟道，并且在制造三极管期间用作自对准掩模，以将N +和P +掺杂精确对准到多晶硅栅极配置。 SOI具有非常薄的N掺杂层，其中N +和P +掺杂以相继不同的能级逐步施加，使得掺杂完全延伸穿过N层，并且在层的整个厚度上是均匀的。 N沟道窄，并且具有SOI衬底的晶体硅最上层的厚度的至少两倍的宽度。

公开(公告)号：US5527721A

公开(公告)日：1996-06-18

申请号：US517801

申请日：1995-08-22

申请人： Joseph E. Farb

发明人： Joseph E. Farb

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/49 ,  H01L21/8234

CPC分类号： H01L29/4983 ,  H01L29/1083 ,  H01L29/6659

摘要： A polysilicon gate (42) of an N-channel MOSFET (40) includes a P+ doped central portion (42a), and N+ doped lateral portions (42b,42c) which face an N-type source (24c) and drain (26c) respectively. An N-type dopant is implanted into the surface portion of a P-type channel region (18) to reduce the surface doping and adjust the transistor threshold voltage to approximately 0.8 volts. The lowered channel doping reduces the electric field at the drain (26c) and suppresses injection of hot electrons from the drain (26c) into the gate oxide (14), and also reduces the electric field across the gate oxide (14) and suppresses charging thereof by hot electrons. N-type and P-type graded strata (26a,26b) are formed between the drain (26c) and substrate (12) and create two reverse biased diode junctions which block flow of drain current from the channel region (18), thereby eliminating the creation of hot electrons and impact ionization in the bulk portion of the drain diode, and channel charge carriers through the surface portion of the channel region (18). The surface portions of the channel region (18), drain (26c) and graded strata (26a,26b) are shorted together to form a shorting surface channel through which the charge carriers are constrained to flow.

摘要翻译： N沟道MOSFET（40）的多晶硅栅极（42）包括P +掺杂中心部分（42a），N +掺杂侧面部分（42b，42c）面向N型源极（24c）和漏极（26c） 分别。 将N型掺杂剂注入到P型沟道区（18）的表面部分中以减小表面掺杂，并将晶体管阈值电压调节到大约0.8伏。 降低的沟道掺杂减少了漏极（26c）处的电场，并且抑制了从漏极（26c）到栅极氧化物（14）的热电子的注入，并且还减少了栅极氧化物（14）上的电场并抑制了充电 通过热电子。 在漏极（26c）和衬底（12）之间形成N型和P型渐变层（26a，26b），并产生阻挡漏极电流从沟道区（18）流出的两个反向偏置二极管结，从而消除 在漏极二极管的本体部分中产生热电子和冲击电离，以及通道电荷载流子穿过沟道区（18）的表面部分。 沟道区域（18），漏极（26c）和渐变层（26a，26b）的表面部分被短路在一起形成短路表面通道，电荷载流子通过该短路表面通道被限制流动。

公开(公告)号：US5260227A

公开(公告)日：1993-11-09

申请号：US981032

申请日：1992-11-24

申请人： Joseph E. Farb ,  Kuan Y. Liao ,  Maw-Rong Chin

发明人： Joseph E. Farb ,  Kuan Y. Liao ,  Maw-Rong Chin

IPC分类号： H01L29/80 ,  H01L21/335 ,  H01L21/265

CPC分类号： H01L29/66416

摘要： A method of fabricating self aligned static induction transistors. The method comprises fabricating an N silicon on N.sup.- silicon substrate having an active area. A guard ring is formed around the active area. An N.sup.+ polysilicon layer is formed that comprises source and gate regions. An oxide layer is formed on the N.sup.+ polysilicon layer. A second polysilicon layer is formed on the oxide layer. A second oxide layer is formed on the second polysilicon layer which is then masked by a self aligning mask. Trenches are etched into the substrate using the self aligning mask and gate regions are formed at the bottom of the trenches. A first layer of metal (gate metal) is deposited to make contact with the gate regions. A layer of photoresist is deposited and planarized, and the first layer of metal is overetched below the top surface of the trench. Plasma nitride is deposited and planarized, and a polysilicon mask is deposited over the planarized layer of plasma nitride. The polysilicon mask is etched to expose the gate metal disposed on the field. A second layer of metal is deposited to make contact with the source and gate regions. A passivation layer is formed, and interconnection pads are formed that connect the first and second layers of metal. The present method employs a single minimum geometry trench mask. The key features of the transistor are defined by the trench mask and related processing parameters. Because of the self alignment achieved by the present invention, the number of channels per unit area is higher, which results in higher transconductance. In addition, some of the parasitic capacitance is eliminated by the present invention, resulting in faster operational speed. The variable sidewall trench oxide thickness allows fabrication of static induction transistors with higher or lower breakdown voltages according to the thickness that is chosen, and for a more graded P gate junction.

公开(公告)号：US5185535A

公开(公告)日：1993-02-09

申请号：US716151

申请日：1991-06-17

申请人： Joseph E. Farb ,  Mei Li ,  Chen-Chi P. Chang ,  Maw-Rong Chin

发明人： Joseph E. Farb ,  Mei Li ,  Chen-Chi P. Chang ,  Maw-Rong Chin

IPC分类号： H01L21/74 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L27/12 ,  H01L21/743 ,  H01L21/84 ,  Y10S257/901

摘要： Complimentary metal oxide silicon transistors fabricated on silicon-on-insulator substrates are configured to allow separately controllable and independent backgate bias for adjacent complimentary devices on the same substrate. By means of deep implantation of boron, a backgate bias P- well (26,126) is positioned on the N-substrate (17,117) at a front surface of the N- substrate behind the N channel transistor of a complimentary pair. The backgate bias P- well (26,126) is provided with an electrical contact (48,148) at the front of the device, as is the N- silicon substrate to enable independent application of separate bias voltage of different polarities and appropriate magnitude.

摘要翻译： 制造在绝缘体上硅衬底上的免费金属氧化物硅晶体管被配置为允许在相同衬底上的相邻互补器件的单独可控和独立的背栅极偏置。 通过深度注入硼，背桥偏压P阱（26,126）位于N衬底前面的N衬底（17,117）上，该衬底位于互补对的N沟道晶体管的后面。 背板偏置P阱（26,126）在器件的前部设置有电接触（48,148），如同N沟道硅衬底一样，可独立施加不同极性和适当大小的单独偏置电压。

公开(公告)号：US5028564A

公开(公告)日：1991-07-02

申请号：US352583

申请日：1989-04-27

申请人： Chen-Chi P. Chang ,  Kuan Y. Liao ,  Joseph E. Farb

发明人： Chen-Chi P. Chang ,  Kuan Y. Liao ,  Joseph E. Farb

IPC分类号： H01L21/205 ,  H01L21/225 ,  H01L21/8238 ,  H01L21/86 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L21/86 ,  H01L21/2255 ,  Y10S148/031 ,  Y10S148/044

摘要： Methods of fabricating heavily doped edges of mesa structures in silicon-on-sapphire and silicon-on-insulator semiconductor devices. The methods are self-aligning and require a minimum of masking steps to achieve. The disclosed methods reduce edge leakage and resolve N-channel threshold voltage instability problems. Mesa structures are formed that comprise N-channel and P-channel regions having a thermal oxide layer deposited thereover. A doping layer of borosilicate glass, or alternatively, an undoped oxide layer that is subsequently implanted, is deposited over the mesa structures. In the first method, the doping layer is etched by means of an anisotropic plasma etching procedure to form oxide spacers at the edges of the mesa structures. The doping layer is removed from the N-mesa structures using an N-channel mask and wet oxide etching procedure. The structure is then heated to a relatively high temperature to drive the dopant into the edges of the N-channel mesa structures. The protective layers are then removed by a wet etching procedure. The semiconductor device is fabricated to completion in a conventional manner thereafter. In the second method, a nitride layer is deposited over the mesa structures and thermal oxide layer. A thin oxide layer, which is generally deposited by means of a chemical vapor deposition procedure, is deposited over the silicon nitride layer. The formed structure is then processed to expose the N-channel mesa structures. This is accomplished using an N-well mask, the oxide layer is etched to expose the silicon nitride layer over the N-channel, and the nitride layer covering the N-channel is removed by means of hot phosphoric acid using the oxide layer as a mask. The doping layer is then deposited over the mesa structures. This doping layer is then heated to drive the dopant/implant into the edges of the N-channel mesa structures. The doping layer is then removed by wet oxide etching, the nitride layer is removed by rinsing in hot phosphoric acid and the thermal oxide layer is removed by a wet oxide etching procedure. The semiconductor device is again fabricated to completion in a conventional manner thereafter.

公开(公告)号：US5686330A

公开(公告)日：1997-11-11

申请号：US716957

申请日：1996-09-23

申请人： Joseph E. Farb ,  Maw-Rong Chin

发明人： Joseph E. Farb ,  Maw-Rong Chin

IPC分类号： H01L21/76 ,  H01L21/335 ,  H01L29/772 ,  H01L29/80 ,  H01L21/265

CPC分类号： H01L29/66416 ,  H01L29/7722

摘要： A method of fabricating self-aligned static induction transistors is disclosed. The method comprises fabricating a silicon substrate having an active area. A guard ring is formed around the active area. Source and gate regions are formed, and a self-aligned relatively deep trench in accordance with the present invention is formed over the gate regions. This is achieved by forming an oxide layer, and forming a polysilicon layer on the oxide layer. A second oxide layer is formed on the polysilicon layer which is then masked by a self-aligning mask. Trenches are etched into the source and gate regions using the self-aligning mask and gate regions are formed at the bottom of the trenches. The transistors are then processed to completion by forming gate, source and drain regions. This portion of the method comprises the steps of forming maskless self-aligned gate metallization, forming maskless self-aligned contacts to the gate metallization and filling the trench, forming source metallization, and forming a drain contact on the substrate. The method employs a single minimum geometry trench mask. The key features of the transistors are defined by the trench mask and related processing parameters. Because of the self-alignment achieved by the present invention, the number of channels per unit area is higher, which results in higher transconductance. In addition, some parasitic capacitance is eliminated by the present invention, resulting in faster operational speed. The variable sidewall trench oxide thickness allows fabrication of static induction transistors with higher or lower breakdown voltages according to the thickness that is chosen, and for a more graded gate junction.

摘要翻译： 公开了制造自对准静电感应晶体管的方法。 该方法包括制造具有有效面积的硅衬底。 在活动区域​​周围形成保护环。 形成源极和栅极区，并且在栅极区上形成根据本发明的自对准的相对较深的沟槽。 这通过形成氧化物层并在氧化物层上形成多晶硅层来实现。 第二氧化物层形成在多晶硅层上，然后被自对准掩模掩蔽。 使用自对准掩模将沟槽蚀刻到源极和栅极区域中，并且在沟槽的底部形成栅极区域。 然后通过形成栅极，源极和漏极区域来处理晶体管以完成。 该方法的该部分包括以下步骤：形成无掩模自对准栅极金属化，在栅极金属化处形成无掩模自对准接触并填充沟槽，形成源极金属化，并在衬底上形成漏极接触。 该方法采用单个最小几何沟槽掩模。 晶体管的关键特征由沟槽掩模和相关的处理参数来定义。 由于通过本发明实现的自对准，每单位面积的通道数量较多，这导致更高的跨导。 此外，通过本发明消除了一些寄生电容，导致更快的操作速度。 可变侧壁沟槽氧化物厚度允许根据所选择的厚度和更梯度的栅极结制造具有更高或更低击穿电压的静态感应晶体管。

公开(公告)号：US5511036A

公开(公告)日：1996-04-23

申请号：US357825

申请日：1994-12-19

申请人： Joseph E. Farb ,  Chen-chi P. Chang ,  Mei F. Li

发明人： Joseph E. Farb ,  Chen-chi P. Chang ,  Mei F. Li

IPC分类号： H01L29/423 ,  H01L29/788 ,  H01L29/78

CPC分类号： H01L29/7885 ,  H01L29/42324

摘要： Each unit cell (10) of a flash EEPROM array (50) includes a source (18), a drain (20) and a channel (22) formed in a substrate (12). A thin tunnel oxide layer (32) is formed over the substrate (12) and P-Well (14). A bifurcated floating gate (34) is formed on the tunnel oxide layer (32) overlying the channel (22) , and includes a program arm (34a) which overlaps the drain (20), an erase arm (34b) which overlaps the source (18) and a base (34c) which extends around an end of the channel (22) and interconnects the program and erase arms (34a,34b). A thick gate oxide layer (36,36a) is formed over the floating gate (34), and a control gate (38) is formed over the gate oxide layer (36,36a). A central section of the control gate (38) which overlies a gap (34d) between the program and erase arms (34a, 34b) provides threshold voltage control for erasure. The erase arm (34b) spans the entire width of the channel (22), enabling erasure with low applied voltages. The bifurcated floating gate design automatically compensates for alignment error during fabrication such that the relative areas of the channel (22) which underlie the program/erase arms (34a, 34b) and gap (34d) are independent of the location of the gap (34d).

摘要翻译： 闪存EEPROM阵列（50）的每个单元（10）包括源（18），漏极（20）和形成在衬底（12）中的沟道（22）。 在衬底（12）和P阱（14）之上形成薄的隧道氧化物层（32）。 在沟道（22）上的隧道氧化物层（32）上形成有分叉浮动栅极（34），并且包括与漏极（20）重叠的编程臂（34a），与源极重叠的擦除臂（34b） （18）和围绕通道（22）的一端延伸并使编程和擦除臂（34a，34b）互连的基座（34c）。 在浮置栅极（34）上方形成厚栅极氧化层（36,36a），并且在栅极氧化物层（36,36a）上形成控制栅极（38）。 在编程和擦除臂（34a，34b）之间的间隙（34d）上的控制门（38）的中心部分提供用于擦除的阈值电压控制。 擦除臂（34b）跨越通道（22）的整个宽度，能够以低的施加电压进行擦除。 分支浮动门设计在制造期间自动补偿对准误差，使得在编程/擦除臂（34a，34b）和间隙（34d）之下的通道（22）的相对面积与间隙（34d）的位置无关 ）。

公开(公告)号：US5352914A

公开(公告)日：1994-10-04

申请号：US923675

申请日：1992-08-03

申请人： Joseph E. Farb

发明人： Joseph E. Farb

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/49

CPC分类号： H01L29/4983 ,  H01L29/1083 ,  H01L29/6659

摘要： A polysilicon gate (42) of an N-channel MOSFET (40) includes a P+ doped central portion (42a), and N+ doped lateral portions (42b,42c) which face an N-type source (24c) and drain (26c) respectively. An N-type dopant is implanted into the surface portion of a P-type channel region (18) to reduce the surface doping and adjust the transistor threshold voltage to approximately 0.8 volts. The lowered channel doping reduces the electric field at the drain (26c) and suppresses injection of hot electrons from the drain (26c) into the gate oxide (14), and also reduces the electric field across the gate oxide (14) and suppresses charging thereof by hot electrons. N-type and P-type graded strata (26a,26b) are formed between the drain (26c) and substrate (12) and create two reverse biased diode junctions which block flow of drain current from the channel region (18), thereby eliminating the creation of hot electrons and impact ionization in the bulk portion of the drain diode, and channel charge carriers through the surface portion of the channel region (18). The surface portions of the channel region (18), drain (26c) and graded strata (26a,26b) are shorted together to form a shorting surface channel through which the charge carriers are constrained to flow.

摘要翻译： N沟道MOSFET（40）的多晶硅栅极（42）包括P +掺杂中心部分（42a），N +掺杂侧面部分（42b，42c）面向N型源极（24c）和漏极（26c） 分别。 将N型掺杂剂注入到P型沟道区（18）的表面部分中以减小表面掺杂，并将晶体管阈值电压调节到大约0.8伏。 降低的沟道掺杂减少了漏极（26c）处的电场，并且抑制了从漏极（26c）到栅极氧化物（14）的热电子的注入，并且还减少了栅极氧化物（14）上的电场并抑制了充电 通过热电子。 在漏极（26c）和衬底（12）之间形成N型和P型渐变层（26a，26b），并产生阻挡漏极电流从沟道区（18）流出的两个反向偏置二极管结，从而消除 在漏极二极管的本体部分中产生热电子和冲击电离，以及通道电荷载流子穿过沟道区（18）的表面部分。 沟道区域（18），漏极（26c）和渐变层（26a，26b）的表面部分被短路在一起形成短路表面通道，电荷载流子通过该短路表面通道被限制流动。