A binary adding apparatus adds together input words (A0-A7, B0-B7) to produce an output word (E0-E7). The apparatus includes a clock signal generator (CK) and adders (FA0-FA7) each connected to receive bits of equal significance of the input words and all having substantially the same propagation delay, the adders being interconnected in cascaded groups (e.g. FA0, FA1), in the order of significance of the bits of the input words, and the number of adders in each group being such that the total propagation delay through each group is less than the clock period. A first set of latches (A1/1-LA1/12) is connected to outputs of the adders (FA0-FA7), the set comprising respective latches (e.g. LA1/1) each connected to receive a sum bit of respective significance and respective latches (e.g. LA1/3) each connected to receive a carry-out bit from a respective one of the groups. An output set of latches (LA3-1-LA3/9) receives the bits of the output word. The latches of the first and output sets are controlled by the clock generator (CK) whereby all the latches output simultaneously, once per clock period, the bits supplied thereto. A processing assembly connected between the first set of latches and the output set of latches combines, during at least one clock period, the bits outputted by the first set of latches to produce the bits of the output word, the processing assembly including a plurality of logic units (L1-L14) each having a propagation delay which is less than the clock period, and each being operative to carry out one of a plurality of predetermined logic functions (F1-F5).