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公开(公告)号：US5208875A
公开(公告)日：1993-05-04
申请号：US883044
申请日：1992-05-07
CPC分类号： H04N19/433 , G06T1/60 , H04N19/523
摘要： A digital picture signal processing apparatus has memories each capable of storing digital words representing respective pixels which, when arranged in a two-dimensional array, make up a picture. A read address generator produces a digital read address identifying the position of a set of the stored words to be read from respective different ones of the memories, the words of the set representing a set of pixels so positioned relative to one another as to constitute at least some of the pixels of a portion of the picture. The read address comprises at least one least significant bit (LSB) for each of the coordinate directions. A digital filter has a number of multipliers equal to the number of words in the set and each being connected to a data bus of a respective memory so as to receive a respective one of the set of words read therefrom, and a plurality of coefficient memories. Each coefficient memory is connected to a respective one of the multipliers and stores all of a plurality of weighting coefficients each appropriate to the position of a respective one of the set of pixels in the picture portion. Each coefficient memory is responsive to the values of the LSBs and to identification of the memory whose data bus is connected to the associated multiplier to supply to that multiplier that one of the coefficients stored therein appropriate to the position in the picture portion of the pixel represented by the word supplied to that multiplier.
摘要翻译： 数字图像信号处理装置具有各自能够存储表示各个像素的数字字的存储器，当以二维阵列排列时，构成图像。 读取地址生成器产生一个数字读取地址，该数字读取地址识别要从各个不同的存储器读取的存储的字的集合的位置，该集合的字表示相对于彼此定位的一组像素，以构成 图片的一部分的至少一些像素。 读取地址包括用于每个坐标方向的至少一个最低有效位（LSB）。 数字滤波器具有等于集合中的字数并且各自连接到相应存储器的数据总线的多个乘法器，以便接收从其读取的一组字中的相应一个，以及多个系数存储器 。 每个系数存储器连接到相应的一个乘法器，并且存储每个适合于图像部分中的像素组中的相应一个的位置的多个加权系数的全部。 每个系数存储器响应于LSB的值和存储器的识别，其数据总线连接到相关联的乘法器，以向该乘法器提供其中存储的系数之一适合于表示的像素的图像部分中的位置 由提供给该乘数的字。
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公开(公告)号：US5125048A
公开(公告)日：1992-06-23
申请号：US482050
申请日：1990-02-20
CPC分类号： G06T1/60 , H04N19/423 , H04N19/433 , H04N19/523 , H04N19/61 , H04N19/649
摘要： Access to a two-dimensional (2-D) portion of a digital picture signal, the signal being made of a plurality of digital words representing respective pixels (P) when, when arranged in a 2-D array, make up the picture, is achieved as follows. The words are allocated into groups such that the pixels (P) represented by the words of each group make up a 2-D area (T0, T1, etc.) of the picture having a shape and size which is the same for all of the groups, the shape being such that the areas tessellate with one another to constitute at least part of the picture. Each word is stored in one of a plurality of memories (M0 to M15), the number of which is equal to the number of pixels (P) in the 2-D area (T0, T1, etc.), such that, for each pixel position in the area, the words from all of the groups representing the pixels having that pixel position in the area are stored in a respective one of the memories. Then, a set of the stored words which represent a set of pixels are read in parallel. The pixels of the set are so positioned relative to one another as to constitute at least some of the pixels (P0 to P15) of a 2-D portion of the picture which is of the same size and shape as the above-mentioned 2-D area (T0, T1, etc.) whereby, even if the pixels of the set are located in different ones of the 2-D areas, the words representing the pixels (P0 to P15) of the set are each stored in a respective different one of the memories (M0 to M15) so that they can be read in parallel.
摘要翻译： 访问数字图像信号的二维（2-D）部分时，当以2-D阵列排列组成图像时，该信号由表示各个像素（P）的多个数字字组成， 如下实现。 这些字被分配成组，使得由每个组的单词表示的像素（P）构成图像的2-D区域（T0，T1等），其具有与所有图像相同的形状和大小 这些组的形状使得这些区域相互镶嵌以构成图片的至少一部分。 每个字存储在多个存储器（M0至M15）中的一个中，其数量等于2-D区域（T0，T1等）中的像素数（P），使得对于 区域中的每个像素位置，表示具有该区域中的该像素位置的像素的所有组的字被存储在相应的一个存储器中。 然后，并行地读取表示一组像素的一组存储字。 该组的像素相对于彼此如此定位，以便构成图像的2-D部分的至少一些像素（P0至P15），其尺寸和形状与上述2- D区域（T0，T1等），由此即使集合的像素位于2-D区域中的不同区域中，表示集合的像素（P0至P15）的字各自存储在相应的 不同的一个存储器（M0到M15），以便它们可以并行读取。
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公开(公告)号：US5036483A
公开(公告)日：1991-07-30
申请号：US471473
申请日：1990-01-29
申请人： Peter J. Virtue
发明人： Peter J. Virtue
CPC分类号： G06F7/506 , G06F2207/3884
摘要： A binary adding apparatus adds together input words (A0-A7, B0-B7) to produce an output word (E0-E7). The apparatus includes a clock signal generator (CK) and adders (FA0-FA7) each connected to receive bits of equal significance of the input words and all having substantially the same propagation delay, the adders being interconnected in cascaded groups (e.g. FA0, FA1), in the order of significance of the bits of the input words, and the number of adders in each group being such that the total propagation delay through each group is less than the clock period. A first set of latches (A1/1-LA1/12) is connected to outputs of the adders (FA0-FA7), the set comprising respective latches (e.g. LA1/1) each connected to receive a sum bit of respective significance and respective latches (e.g. LA1/3) each connected to receive a carry-out bit from a respective one of the groups. An output set of latches (LA3-1-LA3/9) receives the bits of the output word. The latches of the first and output sets are controlled by the clock generator (CK) whereby all the latches output simultaneously, once per clock period, the bits supplied thereto. A processing assembly connected between the first set of latches and the output set of latches combines, during at least one clock period, the bits outputted by the first set of latches to produce the bits of the output word, the processing assembly including a plurality of logic units (L1-L14) each having a propagation delay which is less than the clock period, and each being operative to carry out one of a plurality of predetermined logic functions (F1-F5).
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