发明授权
US5046023A Graphic processing system having bus connection control capable of
high-speed parallel drawing processing in a frame buffer and a system
memory
失效
具有能够在帧缓冲器和系统存储器中进行高速并行绘制处理的总线连接控制的图形处理系统
- 专利标题: Graphic processing system having bus connection control capable of high-speed parallel drawing processing in a frame buffer and a system memory
- 专利标题(中): 具有能够在帧缓冲器和系统存储器中进行高速并行绘制处理的总线连接控制的图形处理系统
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申请号: US105292申请日: 1987-10-06
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公开(公告)号: US5046023A公开(公告)日: 1991-09-03
- 发明人: Koyo Katsura , Shigeru Matsuo , Jun Sato , Takashi Sone , Yoshikazu Yokota , Masahiko Kikuchi
- 申请人: Koyo Katsura , Shigeru Matsuo , Jun Sato , Takashi Sone , Yoshikazu Yokota , Masahiko Kikuchi
- 申请人地址: JPX Tokyo JPX Ibaraki
- 专利权人: Hitachi, Ltd.,Hitachi Engineering Co., Ltd.
- 当前专利权人: Hitachi, Ltd.,Hitachi Engineering Co., Ltd.
- 当前专利权人地址: JPX Tokyo JPX Ibaraki
- 主分类号: G06T1/20
- IPC分类号: G06T1/20 ; G06T11/20 ; G09G5/02 ; G09G5/393 ; G09G5/399
摘要:
A graphic processing system including a main memory for storing a program and information corresponding to pixels, a main processor for effecting an execution processing of a program transferred from the main memory or from an external device so as to control the system, display/output devices such as a CRT device and a printer for outputting graphic information attained by controlling pixels arranged in a plurality of dimensions, a frame buffer for storing information corresponding to pixels outputted to the display/output devices, and a graphic processor for receiving a command and parameter information transferred from the main memory and/or the main processor, for generating character and graphic data in accordance with a predetermined processing procedure and for performing a transfer control including an execution of a drawing processing to transfer generated data through first and second address buses and first and second data buses to the main memory and/or the frame buffer, respectively. The system also includes bus connection switch circuit to be controlled by the graphic processor to effect a connection control between the first and second address buses and between the first and second data buses so as to enable execution of a drawing processing in the main memory connected to a bus on the main processor side and a data transfer between the main memory and the frame buffer.
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