A method for fabricating a split-gate EPROM cell utilizing stacked etch techniques is provided. In accordance with a preferred embodiment of the method, a layer of silicon dioxide is formed on a P- silicon substrate. A layer of polysilicon is formed on the silicon dioxide layer, followed by growth of an oxide/nitride/oxide (ONO) layer. The ONO and polysilicon layers are etched to define floating gates. Next, an edge of each floating gate is utilized in a self-aligned implant of buried N+ bit lines. The floating gate extends only over a first portion of the channel defined between the adjacent buried bit lines. A differential oxide layer is grown on the substrate between adjacent floating gates in a low temperature steam oxidation step. That is, the oxide formed over the exposed portion of the buried N+ bit line is thicker than the oxide formed over the exposed portion of the channel. Following formation of the differential oxide layer, a second layer of polysilicon is formed and etched to define control lines extending perpendicular to the floating gates in the conventional split-gate EPROM cell structure. The control gates are utilized in a stacked etch to complete the split-gate cells. The etch is carried out such that the oxide overlying the N+ bit lines protect the surface of the substrate, avoiding bit line interruption, while the silicon dioxide overlying the exposed portion of the channel is overetched to form a trench into the channel that extends below the junction depth of the N+ region, thereby eliminating bit line to bit line reach-through.