公开(公告)号：US5721170A

公开(公告)日：1998-02-24

申请号：US484354

申请日：1995-06-07

申请人： Albert M. Bergemont

发明人： Albert M. Bergemont

IPC分类号： H01L21/336 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L29/66659 ,  H01L27/0925 ,  H01L29/7839

摘要： In a high-voltage MOS transistor that utilizes a lightly-doped drain region to isolate a heavily-doped drain region from the substrate, the reverse bias which can be applied across the drain-to-substrate junction of the transistor is increased by reducing the width of the heavily-doped drain region.

摘要翻译： 在利用轻掺杂漏极区域将基底重掺杂漏区隔离的高压MOS晶体管中，可以通过减少晶体管的漏 - 重掺杂漏极区的宽度。

公开(公告)号：US5091327A

公开(公告)日：1992-02-25

申请号：US545396

申请日：1990-06-28

申请人： Albert M. Bergemont

发明人： Albert M. Bergemont

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/7885 ,  Y10S438/981

摘要： A method for fabricating a split-gate EPROM cell utilizing stacked etch techniques is provided. In accordance with a preferred embodiment of the method, a layer of silicon dioxide is formed on a P- silicon substrate. A layer of polysilicon is formed on the silicon dioxide layer, followed by growth of an oxide/nitride/oxide (ONO) layer. The ONO and polysilicon layers are etched to define floating gates. Next, an edge of each floating gate is utilized in a self-aligned implant of buried N+ bit lines. The floating gate extends only over a first portion of the channel defined between the adjacent buried bit lines. A differential oxide layer is grown on the substrate between adjacent floating gates in a low temperature steam oxidation step. That is, the oxide formed over the exposed portion of the buried N+ bit line is thicker than the oxide formed over the exposed portion of the channel. Following formation of the differential oxide layer, a second layer of polysilicon is formed and etched to define control lines extending perpendicular to the floating gates in the conventional split-gate EPROM cell structure. The control gates are utilized in a stacked etch to complete the split-gate cells. The etch is carried out such that the oxide overlying the N+ bit lines protect the surface of the substrate, avoiding bit line interruption, while the silicon dioxide overlying the exposed portion of the channel is overetched to form a trench into the channel that extends below the junction depth of the N+ region, thereby eliminating bit line to bit line reach-through.

公开(公告)号：US5086410A

公开(公告)日：1992-02-04

申请号：US582528

申请日：1990-09-14

申请人： Albert M. Bergemont

发明人： Albert M. Bergemont

IPC分类号： G11C17/00 ,  G11C16/18 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/18

摘要： A semiconductor electrically programmable read only memory (EPROM) contains an array of memory cells that store data which is erased when the EPROM is exposed to radiation, and also contains redundant memory circuitry. The redundant memory circuit includes one or more rows or columns of redundant memory cells. A programmable redundancy control circuit determines, for each row or column of redundant memory cells, which row or column of defective memory cells it will be used to replace. The programmable redundancy control circuit has a plurality of non-erasable EPROM cells. Distinct metal connection lines, formed from a first metal layer, are coupled to the drain region of each non-erasable EPROM cell for detecting the data stored therein. A metal shield, formed from a second metal layer, overlies the non-erasable EPROM cells and the metal connection lines. Further, vertical metal walls coupled to the metal shield at least partially block radiation from entry under the metal shield. The metal shield and vertical metal walls enable the non-erasable EPROM cells in the programmable redundancy control circuit to be permanently programmed so that each row or column of redundant memory cells can be assigned a permanent address.

公开(公告)号：US5604141A

公开(公告)日：1997-02-18

申请号：US293135

申请日：1994-08-19

申请人： Albert M. Bergemont

发明人： Albert M. Bergemont

IPC分类号： H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： In a virtual-ground flash electrically programmable read-only-memory (EPROM), the pitch in the X direction of the floating gates, which are formed over a portion of vertically-adjacent field oxide regions, is reduced by forming the floating gates over continuous strips of vertically-adjacent field oxide. The strips of field oxide are formed in a layer of polysilicon which is formed over a layer of tunnel oxide which, in turn, is formed over the substrate.

摘要翻译： 在虚拟地闪存电可编程只读存储器（EPROM）中，通过在垂直相邻的场氧化物区域的一部分上形成的浮动栅极的X方向上的间距通过形成浮动栅极而减少 垂直相邻的场氧化物的连续条带。 场氧化物条形成在多晶硅层中，多晶硅层形成在隧道氧化物层上，隧道氧化物层又形成在衬底上。

公开(公告)号：US5455790A

公开(公告)日：1995-10-03

申请号：US243466

申请日：1994-05-16

申请人： Michael J. Hart ,  Albert M. Bergemont

发明人： Michael J. Hart ,  Albert M. Bergemont

IPC分类号： G11C16/10 ,  G11C16/14 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/68

CPC分类号： G11C16/10 ,  G11C16/14 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7883 ,  Y10S438/972

摘要： Each byte of data in a high-density, electrically-erasable, programmable read-only-memory (EEPROM) cell array is selectively erased by forming a plurality of memory cells in each of a plurality of P-wells where the memory cells in each P-well are formed one byte wide by n rows in length. By forming the memory cells in each P-well to be one byte wide by n rows in length, each byte of data can be selectively erased by identifying the corresponding P-well and the row within the P-well.

摘要翻译： 通过在多个P阱中的每个P阱中形成多个存储单元来选择性地擦除高密度，电可擦除可编程只读存储器（EEPROM）单元阵列中的每个字节的数据，其中每个P阱中的存储器单元 P-well形成一个字节宽，长度为n行。 通过将每个P阱中的存储单元形成为一个字节宽，长度为n行，可以通过识别P阱中的相应P阱和行来选择性地擦除每个字节的数据。

公开(公告)号：US5453393A

公开(公告)日：1995-09-26

申请号：US318363

申请日：1994-10-05

申请人： Albert M. Bergemont

发明人： Albert M. Bergemont

IPC分类号： G11C16/10 ,  G11C16/14 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/10 ,  G11C16/14 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7883 ,  Y10S438/972

摘要： The memory array of a high density, electrically-erasable, programmable read-only-memory (EEPROM) is divided into a series of segments which are individually accessible via a plurality of segment select transistors. When a specific memory cell or cells is to be read, only the segment select transistors which correspond to the segment of memory which contains the specific memory cell or cells are turned on. As a result, the time required to access the specific memory cell or cells can be significantly reduced.

摘要翻译： 高密度，电可擦除可编程只读存储器（EEPROM）的存储器阵列被分成可以通过多个段选择晶体管单独访问的一系列段。 当要读取特定的存储单元或单元时，只有与包含特定存储单元或存储单元的存储器段对应的段选择晶体管导通。 结果，可以显着地减少访问特定存储器单元或单元所需的时间。

公开(公告)号：US5460990A

公开(公告)日：1995-10-24

申请号：US285650

申请日：1994-08-03

申请人： Albert M. Bergemont

发明人： Albert M. Bergemont

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  G11C16/0491 ,  H01L27/115

摘要： The current driven by the segment select transistors of an alternate-metal, virtual-ground (AMG) electrically programmable read-only-memory (EPROM), is increased by eliminating the even numbered segment select transistors in every other row of segment select transistors, and the odd numbered segment select transistors in the remaining rows, and by changing the current path through the segment so that the current flows from a segment select transistor in one row of segment select transistors to a segment select transistor in an adjacent row of transistors. By eliminating every other segment select transistor in each row of transistors, the maximum pitch of the segment select transistors can be substantially increased, thereby providing the required programming current, while at the same time maintaining the required isolation between adjacent segment select transistors.

摘要翻译： 由替代金属虚拟地（AMG）电可编程只读存储器（EPROM）的段选择晶体管驱动的电流通过消除每隔一行的段选择晶体管中的偶数段选择晶体管而增加， 以及剩余行中的奇数段选择晶体管，并且通过改变通过该段的电流路径，使得电流从一行段选择晶体管中的段选择晶体管流到相邻行晶体管中的段选择晶体管。 通过消除晶体管每行中的每个其它段选择晶体管，可以大幅增加段选择晶体管的最大间距，从而提供所需的编程电流，同时保持相邻段选择晶体管之间所需的隔离。

公开(公告)号：US5409854A

公开(公告)日：1995-04-25

申请号：US213903

申请日：1994-03-15

申请人： Albert M. Bergemont

发明人： Albert M. Bergemont

IPC分类号： H01L21/8247 ,  H01L21/265

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： The floating gate of a virtual-ground flash electrically programmable read-only-memory (EPROM) cell, which is formed over a portion of a pair of vertically-adjacent field oxide regions, is self aligned to the field oxide regions by utilizing a stacked etch process to define the widths of both the floating gate and the field oxide regions. As a result, the pitch of the cells in the X direction can be substantially reduced.

摘要翻译： 在一对垂直相邻的场氧化物区域的一部分上形成的虚拟地闪存电可编程只读存储器（EPROM）单元的浮动栅极通过利用堆叠的场地与场氧化物区域自对准 蚀刻工艺来定义浮动栅极和场氧化物区域的宽度。 结果，可以显着地减小电池在X方向的间距。

公开(公告)号：US5402372A

公开(公告)日：1995-03-28

申请号：US152408

申请日：1993-11-15

申请人： Albert M. Bergemont

发明人： Albert M. Bergemont

IPC分类号： G11C16/10 ,  G11C16/14 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C8/00

CPC分类号： G11C16/10 ,  G11C16/14 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7883 ,  Y10S438/972

摘要： The memory array of a high density, electrically-erasable, programmable read-only-memory (EEPROM) is divided into a series of segments which are individually accessible via a plurality of segment select transistors. When a specific memory cell or cells is to be read, only the segment select transistors which correspond to the segment of memory which contains the specific memory cell or cells are turned on. As a result, the time required to access the specific memory cell or cells can be significantly reduced.

摘要翻译： 高密度，电可擦除可编程只读存储器（EEPROM）的存储器阵列被分成可以通过多个段选择晶体管单独访问的一系列段。 当要读取特定的存储单元或单元时，只有与包含特定存储单元或存储单元的存储器段对应的段选择晶体管导通。 结果，可以显着地减少访问特定存储器单元或单元所需的时间。

公开(公告)号：US5212541A

公开(公告)日：1993-05-18

申请号：US687281

申请日：1991-04-18

申请人： Albert M. Bergemont

发明人： Albert M. Bergemont

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L29/7885

摘要： The present invention provides a 5V only, EPROM memory cell structure that is utilizable in high speed UV-erasable or flash EPROM contactless arrays and that uses source side injection for programming. The EPROM cell structure comprises spaced-apart N-type source and drain regions that define a channel region in a P-type substrate. A first layer of insulating material overlies the channel region. A polysilicon (poly 1) floating gate is formed on the first insulating layer and overlies a first portion of the channel region that extends from the drain region to a point in the channel region intermediate the source and drain regions thereby defining a second portion of the channel region that extends from the intermediate point to the source region and over which the floating gate does not extend. The poly 1 floating gate also includes a coupling portion that extends over the field oxide that defines the active device area in which the EPROM cell is formed. A second layer of insulating material is formed over the floating gate, including the coupling portion of the floating gate. A polysilicon (poly 2) control gate overlies the floating gate but is separated therefrom by the second insulating layer. The poly 2 control gate includes an access portion that overlies the second portion of the channel region but is separated therefrom by the first layer of insulating material. A polysilicon (poly 2) coupling line overlies the coupling portion of the floating gate but is separated therefrom by the second insulating layer. This cell structure is utilized in a contactless array that relies on shared source lines, resulting in very small cell size and relatively simple decoding.