发明授权
- 专利标题： Integrated circuit device provided with test mode function
- 专利标题（中）： 具有测试模式功能的集成电路设备
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申请号： US571852申请日： 1990-08-24
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公开(公告)号： US5103167A公开(公告)日： 1992-04-07
- 发明人: Nobuhiro Okano , Hiroshi Uemura , Eiji Ogino
- 申请人： Nobuhiro Okano , Hiroshi Uemura , Eiji Ogino
- 申请人地址： JPX
- 专利权人： Sharp Kabushiki Kaisha
- 当前专利权人： Sharp Kabushiki Kaisha
- 当前专利权人地址： JPX
- 优先权： JPX1-225927 19890831
- 主分类号： G01R31/28
- IPC分类号： G01R31/28 ; G01R31/317 ; G06F11/22 ; G06F15/78 ; H01L21/822 ; H01L27/04
摘要：
An integrated circuit device provided with test mode function has a plurality of terminals used for receiving and/or feeding out signals during a normal operation of the device. At least one terminal of the plurality of terminals are connected to a register for storing test mode setting data applied through the at least one terminal during a reset cycle period of the device. In accordance with the test mode setting data stored in the register, a setting of a predetermined test mode of the device is executed.
公开/授权文献
- US4012810A Drawing system arrangement for spinning machines 公开/授权日：1977-03-22
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