发明授权
US5117488A Microprogram controlled microprocessor having a selectively expandable
instruction code length including independent description of operand
addressing and a type of operation for an operand by single instruction
in a common coding scheme
失效
具有可选择的可扩展指令码长度的微控制微控制器，其中包括独立的操作说明和通用编程方案中的单个操作的操作类型
- 专利标题： Microprogram controlled microprocessor having a selectively expandable instruction code length including independent description of operand addressing and a type of operation for an operand by single instruction in a common coding scheme
- 专利标题（中）： 具有可选择的可扩展指令码长度的微控制微控制器，其中包括独立的操作说明和通用编程方案中的单个操作的操作类型
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申请号： US265539申请日： 1988-11-01
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公开(公告)号： US5117488A公开(公告)日： 1992-05-26
- 发明人: Kouki Noguchi , Fumio Tsuchiya , Takashi Tsukamoto , Shigeki Masumura , Hideo Nakamura , Shiro Baba , Yoshimune Hagiwara
- 申请人： Kouki Noguchi , Fumio Tsuchiya , Takashi Tsukamoto , Shigeki Masumura , Hideo Nakamura , Shiro Baba , Yoshimune Hagiwara
- 申请人地址： JPX Tokyo JPX Tokyo JPX Tokyo
- 专利权人： Hitachi, Ltd.,Hitachi Microcomputer Engineering Ltd.,VLSI Engineering Corporation
- 当前专利权人： Hitachi, Ltd.,Hitachi Microcomputer Engineering Ltd.,VLSI Engineering Corporation
- 当前专利权人地址： JPX Tokyo JPX Tokyo JPX Tokyo
- 优先权： JPX62-277410 19871104
- 主分类号： G06F9/22
- IPC分类号： G06F9/22 ; G06F9/26 ; G06F9/30
摘要：
In a microprocessor, a minimum instruction code length is set to a predetermined number of bits (e.g. one byte) length. One feature of the invention is that an instruction set which can selectively expand the instruction code length at a unit of the predetermined number of bits is used. Another feature is that an operand addressing mode and a type of operation for an operand are designated by separate predetermined number of code bits which are coded in a common coding scheme so that an instruction decoder is shared by those codes.
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