Invention Grant
US5138203A Integrated circuit compensation for losses in signal lines due to parasitics 失效
由于寄生效应引起的信号线损耗的集成电路补偿

Integrated circuit compensation for losses in signal lines due to
parasitics
Abstract:
An integrated circuit including a plurality of circuits having the same input impedance, arranged at regular intervals, and applied with a signal from a single signal source, is disclosed in which the input impedance is substantially capacitive, the characteristic impedance of a signal line connected to the signal source for sending the signal to the circuits is given by Z.sub.0 .sqroot.L/C, where L indicates the inductance of the signal line per one circuit, and C indicates the combined capacitance of the parasitic capacitance of the signal line per one circuit and the input capacitance of each circuit, the signal line is terminated by a circuit element having impedance equal to the characteristic impedance Z.sub.0, and the signal source has output impedance equal to the characteristic impedance Z.sub.0.
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