公开(公告)号：US5138203A

公开(公告)日：1992-08-11

申请号：US342328

申请日：1989-04-24

申请人： Koichi Ono ,  Masao Hotta ,  Yoshito Nejime

发明人： Koichi Ono ,  Masao Hotta ,  Yoshito Nejime

IPC分类号： H03M1/36 ,  H03K17/16 ,  H03K17/60 ,  H03K19/0175 ,  H03M1/06

CPC分类号： H03M1/06 ,  H03K17/16 ,  H03K17/603 ,  H03M1/365

摘要： An integrated circuit including a plurality of circuits having the same input impedance, arranged at regular intervals, and applied with a signal from a single signal source, is disclosed in which the input impedance is substantially capacitive, the characteristic impedance of a signal line connected to the signal source for sending the signal to the circuits is given by Z.sub.0 .sqroot.L/C, where L indicates the inductance of the signal line per one circuit, and C indicates the combined capacitance of the parasitic capacitance of the signal line per one circuit and the input capacitance of each circuit, the signal line is terminated by a circuit element having impedance equal to the characteristic impedance Z.sub.0, and the signal source has output impedance equal to the characteristic impedance Z.sub.0.

摘要翻译： 公开了一种集成电路，其包括具有相同输入阻抗的多个电路，以规则的间隔布置并且施加了来自单个信号源的信号，其中输入阻抗基本上是电容性的，信号线的特性阻抗连接到 用于将信号发送到电路的信号源由Z0 2ROOT L / C给出，其中L表示每个电路的信号线的电感，C表示每个电路的信号线的寄生电容的组合电容， 每个电路的输入电容，信号线由具有等于特性阻抗Z0的阻抗的电路元件端接，并且信号源具有等于特性阻抗Z0的输出阻抗。

公开(公告)号：US4866444A

公开(公告)日：1989-09-12

申请号：US154086

申请日：1988-02-09

申请人： Yoshito Nejime ,  Masao Hotta ,  Kenji Maio ,  Koichi Ono

发明人： Yoshito Nejime ,  Masao Hotta ,  Kenji Maio ,  Koichi Ono

IPC分类号： H03M1/36 ,  H03M1/00 ,  H03M1/12

CPC分类号： H03M1/0809 ,  H03M1/365

摘要： A flash type AD converter includes a group of comparators divided into blocks each including 2.sup.N comparators (N=1, 2, ---), each comparing an input signal with one of a plurality of reference signals, each having individually different voltage levels. One of the comparators may correspond to a level change point where the voltage level of the input signal is higher than that of the reference signal of that comparator which then generates a specific output different from those of the remaining comparators. The converter generates a binary-coded output on the basis of the specific output generated from the level change point comparator. When any one of the plural comparators belonging to one of the blocks generates the specific output, the specific output is applied as an inhibit signal to inhibit appearance of an output from a block including comparators having reference voltage signals with corresponding levels lower than those of the comparators of the block to which the comparator generating the specific output belongs.

摘要翻译： 闪光型AD转换器包括一组比较器，其被分成块，每个块包括2N个比较器（N = 1,2，...），每个比较器将输入信号与多个参考信号中的一个进行比较，每个参考信号具有单独不同的电压电平。 一个比较器可以对应于电平变化点，其中输入信号的电压电平高于该比较器的参考信号的电平，然后产生与剩余的比较器不同的特定输出。 转换器根据从电平变化点比较器产生的特定输出产生二进制编码输出。 当属于其中一个块的多个比较器中的任何一个产生特定输出时，该特定输出被施加作为禁止信号，以抑制来自包括比较器的输出的出现，该比较器具有的参考电压信号的相应电平低于 生成特定输出的比较器所属的块的比较器。

公开(公告)号：US4978957A

公开(公告)日：1990-12-18

申请号：US475799

申请日：1990-02-06

申请人： Masao Hotta ,  Toshihiko Shimizu ,  Yoshito Nejime

发明人： Masao Hotta ,  Toshihiko Shimizu ,  Yoshito Nejime

IPC分类号： H03M1/14 ,  H03M1/36

CPC分类号： H03M1/147 ,  H03M1/365

摘要： Disclosed is a parallel analog-to-digital converter in which a plurality of comparators are divided into a plurality of groups each consisting of a predetermined number of comparators, and outputs of at least these comparators belonging to the same group are added in an analog or digital fashion. Whether or not the result of addition of the outputs of the comparators exceeds a predetermined threshold level is decided in an analog or digital fashion so as to determine high-order and low-order bits of a digital output signal of the converter on the basis of the result of decision.

摘要翻译： 公开了一种并行模拟 - 数字转换器，其中多个比较器被分成多个组，每个组由预定数量的比较器组成，并且至少属于同一组的这些比较器的输出被添加到模拟或 数码时尚。 以模拟或数字的方式决定比较器的输出的相加结果是否超过预定阈值水平，以便基于以下方式确定转换器的数字输出信号的高阶和低位： 决定的结果。

公开(公告)号：US06226605B1

公开(公告)日：2001-05-01

申请号：US09132214

申请日：1998-08-11

申请人： Yoshito Nejime ,  Hiroshi Ikeda ,  Masao Hotta

发明人： Yoshito Nejime ,  Hiroshi Ikeda ,  Masao Hotta

IPC分类号： G10L1104

CPC分类号： H04R25/505 ,  G10L21/0232 ,  G10L21/0364 ,  G10L21/04 ,  H04R1/005 ,  H04R5/04 ,  H04R25/70 ,  H04R2205/041 ,  H04R2225/43

摘要： Making use of a digital acoustic signal processing apparatus arranged by employing memory device for storing a digital acoustic signal, acoustic frequency feature enhancing device for enhancing an acoustic frequency feature, and low-speed sound reproducing device for changing a speed of the stored voice to reproduce this voice as a low speed into a hearing aid and an appliance with an acoustic output, a hearing function difficulty due to an age is aided in utilization of audio output appliances such as a hearing aid, television receiver, and a telephone receiver. After the voice has been stored in the memory device, a process for enhancing the frequency characteristic in order to fit the frequency characteristic to the individual hearing characteristic and the voice reproducing environment is carried out and thereafter represented to the user. The user can repeatedly listen the voice stored in the memory device with employment of control device for controlling the voice reproducing operation. Furthermore, since a process for expanding a time scale during a sound reproducing operation is carried out, the voice can be represented at the low speed. Since the voice whose frequency characteristic has been enhanced can be represented at the low speed in order that either an individual hearing ability, or an apparatus is fitted to a using environment, hearing articulation can be improved with respect to such a hearing, the frequency resolution and the time resolution are simultaneously deteriorated.

摘要翻译： 利用通过采用用于存储数字声音信号的存储装置而布置的数字声信号处理装置，用于增强声频特征的声频特征增强装置和用于改变所存储的声音的速度以便再现的低速声音再现装置 这种声音作为低速进入助听器和具有声学输出的器具，由于年龄而引起的听力功能困难有助于使用诸如助听器，电视接收机和电话接收器的音频输出设备。 在语音已被存储在存储装置中之后，执行用于增强频率特性以便将频率特性适应于个人听觉特性和语音再现环境的过程，并且此后表示给用户。 用户可以通过使用用于控制语音再现操作的控制装置来重复监听存储在存储设备中的语音。 此外，由于执行在声音再现操作期间扩展时标的处理，所以可以以低速表示声音。 由于频率特性已被增强的声音可以以低速表示，以便将单独的听觉能力或装置安装在使用环境中，可以相对于这种听觉改善听觉发音，频率分辨率 并且时间分辨率同时恶化。

公开(公告)号：US5794201A

公开(公告)日：1998-08-11

申请号：US462268

申请日：1995-06-05

申请人： Yoshito Nejime ,  Hiroshi Ikeda ,  Masao Hotta

发明人： Yoshito Nejime ,  Hiroshi Ikeda ,  Masao Hotta

IPC分类号： G10L21/02 ,  G10L21/0232 ,  G10L21/04 ,  H04R1/00 ,  H04R5/04 ,  H04R25/00 ,  G10L3/00 ,  G10L3/02 ,  G10L9/00

CPC分类号： H04R25/505 ,  G10L21/0364 ,  G10L21/04 ,  H04R1/005 ,  H04R5/04 ,  G10L21/0232 ,  H04R2205/041 ,  H04R2225/43 ,  H04R25/70

摘要： Making use of a digital acoustic signal processing apparatus arranged by employing memory device for storing a digital acoustic signal, acoustic frequency feature enhancing device for enhancing an acoustic frequency feature, and low-speed sound reproducing device for changing a speed of the stored voice to reproduce this voice as a low speed into a hearing aid and an appliance with an acoustic output, a hearing function difficulty due to an age is aided in utilization of audio output appliances such as a hearing aid, television receiver, and a telephone receiver. After the voice has been stored in the memory device, a process for enhancing the frequency characteristic in order to fit the frequency characteristic to the individual hearing characteristic and the voice reproducing environment is carried out and thereafter represented to the user. The user can repeatedly listen the voice stored in the memory device with employment of control device for controlling the voice reproducing operation. Furthermore, since a process for expanding a time scale during a sound reproducing operation is carried out, the voice can be represented at the low speed. Since the voice whose frequency characteristic has been enhanced can be represented at the low speed in order that either an individual hearing ability, or an apparatus is fitted to a using environment, hearing articulation can be improved with respect to such a hearing, the frequency resolution and the time resolution are simultaneously deteriorated.

摘要翻译： 利用通过采用用于存储数字声音信号的存储装置而布置的数字声信号处理装置，用于增强声频特征的声频特征增强装置和用于改变所存储的声音的速度以便再现的低速声音再现装置 这种声音作为低速进入助听器和具有声学输出的器具，由于年龄而引起的听力功能困难有助于使用诸如助听器，电视接收机和电话接收器的音频输出设备。 在语音已被存储在存储装置中之后，执行用于增强频率特性以便将频率特性适应于个人听觉特性和语音再现环境的过程，并且此后表示给用户。 用户可以通过使用用于控制语音再现操作的控制装置来重复监听存储在存储设备中的语音。 此外，由于执行在声音再现操作期间扩展时标的处理，所以可以以低速表示声音。 由于频率特性已被增强的声音可以以低速表示，以便将单独的听觉能力或装置安装到使用环境中，可以相对于这种听觉改善听觉发音，频率分辨率 并且时间分辨率同时恶化。

公开(公告)号：US4939518A

公开(公告)日：1990-07-03

申请号：US248374

申请日：1988-09-23

申请人： Masao Hotta ,  Toshihiko Shimizu ,  Kenzi Maio ,  Yoshito Nejime

发明人： Masao Hotta ,  Toshihiko Shimizu ,  Kenzi Maio ,  Yoshito Nejime

IPC分类号： H03M1/12 ,  H03M1/20 ,  H03M1/36

CPC分类号： H03M1/206 ,  H03M1/1235 ,  H03M1/365

摘要： In a cyclic averaging analog to digital converter, reference voltages having a plurality of levels, each of which is inputted to one of a plurality of comparators in a flash type analog to digital converter, are shifted cyclically by a small voltage, and the outputs of the flash type analog to digital converter are added for every shift cycle in order to obtain an output digital signal. The outputs of a voltage dividing circuit provide the reference voltages with N levels, the levels differing cyclically by a small voltage. The N reference voltages are divided into groups, each of which consists of M elements N/M, switches are provided each of which selects one of the reference voltages one after another for an associated group N/M reference voltages are thus selected by these switches and are supplied to the comparators.

摘要翻译： 在循环平均模数转换器中，具有多个电平的参考电压，每个电平被输入到闪存类型模数转换器中的多个比较器中的一个，周期性地被小电压移位，并且输出 为每个移位周期添加闪存型模数转换器，以获得输出数字信号。 分压电路的输出为N个电平提供参考电压，该电平周期性地受到小电压的限制。 N个参考电压被分成组，每个组由M个元件N / M组成，提供开关，每个选择一个参考电压一个接一个地为相关联的组N / M参考电压由这些开关选择 并提供给比较器。

公开(公告)号：US5534864A

公开(公告)日：1996-07-09

申请号：US12759

申请日：1993-02-03

申请人： Koichi Ono ,  Yoshito Nejime ,  Etsuji Yamamoto

发明人： Koichi Ono ,  Yoshito Nejime ,  Etsuji Yamamoto

IPC分类号： H03M1/14 ,  H03M1/06 ,  H03M1/16

CPC分类号： H03M1/0695 ,  H03M1/167

摘要： A pipelined A/D converter which minimizes differential non-linearity by preventing mismatching between converting stages. The A/D converter includes a plurality of converting stages connected in a cascade form wherein each of the converting stages includes an ADC unit for converting an analog input into a digital output. The digital outputs from said converting stages form a conversion output. Each preceding converting stage except a last converting stage further includes an amplifier for deriving and amplifying a conversion residue representing a quantization error resulting from the conversion performed by the preceding converting stage based on the digital output outputted by the ADC unit of the preceding converting stage and the analog input inputted to the preceding converting stage. The amplified conversion residue from the preceding converting stage is supplied as an analog input to a succeeding converting stage. A connector is provided for connecting the amplifier of the preceding converting stage to a node in the ADC unit of the succeeding converting stage. The node provides a base voltage to the ADC unit of the succeeding converting stage.

摘要翻译： 一种流水线A / D转换器，通过防止转换级之间的失配使差分非线性最小化。 A / D转换器包括以级联形式连接的多个转换级，其中每个转换级包括用于将模拟输入转换为数字输出的ADC单元。 来自所述转换级的数字输出形成转换输出。 除了最后的转换级之外的每个前一转换级还包括放大器，用于根据由前一转换级的ADC单元输出的数字输出，导出并放大表示由前一转换级进行的转换而产生的量化误差的转换余数，以及 输入到前一转换级的模拟输入。 来自前一转换级的放大的转换余数作为模拟输入提供给后续转换级。 提供连接器，用于将前一转换级的放大器连接到后续转换级的ADC单元中的节点。 节点为后续转换级的ADC单元提供基极电压。

公开(公告)号：US06529632B1

公开(公告)日：2003-03-04

申请号：US09516207

申请日：2000-02-29

申请人： Yuichiro Nakaya ,  Yoshito Nejime

发明人： Yuichiro Nakaya ,  Yoshito Nejime

IPC分类号： G06K936

CPC分类号： H04N19/44 ,  G06T7/223 ,  G06T7/262 ,  G06T9/004 ,  H04N19/105 ,  H04N19/114 ,  H04N19/115 ,  H04N19/117 ,  H04N19/124 ,  H04N19/126 ,  H04N19/127 ,  H04N19/139 ,  H04N19/159 ,  H04N19/16 ,  H04N19/172 ,  H04N19/176 ,  H04N19/177 ,  H04N19/18 ,  H04N19/182 ,  H04N19/184 ,  H04N19/186 ,  H04N19/19 ,  H04N19/45 ,  H04N19/46 ,  H04N19/50 ,  H04N19/51 ,  H04N19/513 ,  H04N19/52 ,  H04N19/521 ,  H04N19/523 ,  H04N19/547 ,  H04N19/573 ,  H04N19/577 ,  H04N19/587 ,  H04N19/59 ,  H04N19/597 ,  H04N19/61 ,  H04N19/625 ,  H04N19/86 ,  H04N19/90 ,  H04N19/94

摘要： An image coding method includes the steps of storing a reference image which is a decoded image of an image previously coded based on a first prediction image synthesized by performing motion compensation, estimating motion vectors based on a comparison of an input image to be coded and the reference image, and synthesizing a second prediction image by performing motion compensation using the motion vectors and the reference image. A rounding method used for pixel value interpolation in performing the motion compensation for synthesizing the first prediction image is one of a positive rounding method and a negative rounding method, and a rounding method used for pixel value interpolation in performing the motion compensation for synthesizing the second prediction image is a different one of the positive rounding method and the negative rounding method.

摘要翻译： 一种图像编码方法包括以下步骤：存储作为基于通过执行运动补偿合成的第一预测图像的先前编码的图像的解码图像的参考图像，基于要编码的输入图像的比较估计运动矢量， 参考图像，并且通过使用运动矢量和参考图像执行运动补偿来合成第二预测图像。 用于执行用于合成第一预测图像的运动补偿的像素值插值的舍入方法是正舍入方法和负舍入方法之一，以及用于执行用于合成第二预测图像的运动补偿的像素值内插的舍入方法 预测图像是正圆舍入法和负舍入法中不同的一种。

公开(公告)号：US06407776B1

公开(公告)日：2002-06-18

申请号：US09506809

申请日：2000-02-18

申请人： Nobuhiro Sekimoto ,  Yoshito Nejime ,  Takashi Hasegawa ,  Yasuhiro Akiyama

发明人： Nobuhiro Sekimoto ,  Yoshito Nejime ,  Takashi Hasegawa ,  Yasuhiro Akiyama

IPC分类号： H04N5445

CPC分类号： H04N5/44513 ,  H04N5/44543 ,  H04N21/4122 ,  H04N21/4143 ,  H04N21/42661 ,  H04N21/4325 ,  H04N21/4334 ,  H04N21/4622 ,  H04N21/47214 ,  H04N21/47217 ,  H04N21/84

摘要： A method of displaying program-related information while the user views a program video mainly and a broadcasting program displaying device to implement the method without making the user's operation complicated and confusing. A picture plane is constructed by two picture planes having a television picture plane (picture plane 1) for displaying the program video which is outputted from a broadcasting program displaying device and further a property state picture plane as another picture plane (picture plane 2). The program video is displayed to the picture plane 1 and an operation picture plane of the broadcasting program displaying device and the program related-information are displayed to the picture plane 2. A broadcasting program displaying device for two-screen construction has functions for display, recording, replay, reservation recording, and the like in response to an instruction from a device which the user operates.

摘要翻译： 在用户主要观看节目视频时显示节目相关信息的方法以及广播节目显示装置来实现该方法而不使用户的操作变得复杂和混乱。 由具有电视画面（画面1）的两个画面构成画面，用于显示从广播节目显示装置输出的节目视频，另外还有属性状态画面作为另一画面（画面2）。 节目视频被显示到画面1，并且广播节目显示装置的操作画面和节目相关信息被显示到画面2.具有用于两画面结构的广播节目显示装置具有显示功能， 记录，重放，预约记录等，以响应来自用户操作的设备的指令。

公开(公告)号：US5004932A

公开(公告)日：1991-04-02

申请号：US373261

申请日：1989-06-27

申请人： Yoshito Nejime

发明人： Yoshito Nejime

IPC分类号： G06G7/60 ,  G06F15/18 ,  G06N3/06 ,  G06N3/063 ,  G06N99/00 ,  H03K19/00

CPC分类号： G06N3/063 ,  G06N3/0635

摘要： A semiconductor integrated circuit for constructing a neural network model, comprising a differential amplifier which includes one output terminal and two input terminals, an excitatory synapse circuit which is connected to the noninverting input terminal of said differential amplifier, and an inhibitory synapse circuit which is connected to the inverting input terminal of said differential amplifier, wherein each of said excitatory and inhibitory synapse circuits includes a plurality of current switches, regulated current source ciruits which are equal in number to said current switches and which determine currents to flow through said current switches, and one load resistor which is connected to all of said current switches, input terminals of said each synapse circuit being constructed of terminals which turn "on" and "off" the respective current switches and to which external inputs or outputs of another neural circuit are connected, said each regulated current source circuit being constructed of a circuit whose current value can be increased or decreased by a voltage externally applied separately and as to which a value of the voltage for increasing or decreasing the current value corresponds to a synaptic weight.