发明授权
US5166604A Methods and apparatus for facilitating scan testing of asynchronous
logic circuitry
失效
用于促进异步逻辑电路的扫描测试的方法和装置
- 专利标题: Methods and apparatus for facilitating scan testing of asynchronous logic circuitry
- 专利标题(中): 用于促进异步逻辑电路的扫描测试的方法和装置
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申请号: US611974申请日: 1990-11-13
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公开(公告)号: US5166604A公开(公告)日: 1992-11-24
- 发明人: Bahram Ahanin , Craig S. Lytle , Ricky W. Ho
- 申请人: Bahram Ahanin , Craig S. Lytle , Ricky W. Ho
- 申请人地址: CA San Jose
- 专利权人: Altera Corporation
- 当前专利权人: Altera Corporation
- 当前专利权人地址: CA San Jose
- 主分类号: G01R31/317
- IPC分类号: G01R31/317 ; G01R31/3185
摘要:
Scan testing of asynchronous logic circuitry is facilitated by gating off the asynchronous inputs to flip-flops during scan testing. If desired, the asynchronous inputs which are gated off in this manner may themselves terminals or scan registers during testing. Alternatively, the asynchronous inputs which are gated could be tested by selectively enabling the signals at strategic points during scan testing. The number of input terminals required to control the test mode may be reduced by providing registers for storing test control signals applied to normal input terminals at the beginning of a test cycle. Once these test control signals are stored, the normal input terminals are free to return to their normal use.
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