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    Programmable logic array integrated circuits
    2.
    发明授权
    Programmable logic array integrated circuits 失效
    可编程逻辑阵列集成电路

    公开(公告)号：US5668771A

    公开(公告)日：1997-09-16

    申请号：US655870

    申请日：1996-05-24

    申请人： Richard G. Cliff ,  L. Todd Cope ,  Cameron R. McClintock ,  William Leong ,  James A. Watson ,  Joseph Huang ,  Bahram Ahanin

    发明人： Richard G. Cliff ,  L. Todd Cope ,  Cameron R. McClintock ,  William Leong ,  James A. Watson ,  Joseph Huang ,  Bahram Ahanin

    IPC分类号： G01R31/3185 ,  G11C8/12 ,  H03K19/094 ,  H03K19/173 ,  H03K19/177 ,  G11C13/00 ,  G11B7/00

    CPC分类号： H03K19/09429 ,  G11C8/12 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/1776 ,  H03K19/1778 ,  H03K19/17792 ,  G01R31/318516

    摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

    摘要翻译： 可编程逻辑阵列集成电路具有多个可编程逻辑模块，它们被组合在多个逻辑阵列块（“LAB”）中。 LAB以二维阵列布置在电路上。 提供一个导线网络，用于将任何逻辑模块与任何其他逻辑模块相互连接。 此外，相邻或附近的逻辑模块可以彼此连接，用于在逻辑模块之间提供进位链和/或用于将两个或多个模块连接在一起以提供更复杂的逻辑功能而不必利用一般互连的特殊目的 网络。 提供了所谓的快速或通用导体的另一网络，用于在整个电路中分布广泛使用的逻辑信号，例如时钟和清除信号。 多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。

    PLD with selective inputs from local and global conductors
    5.
    发明授权
    PLD with selective inputs from local and global conductors 失效
    PLD具有来自本地和全球导体的选择性输入

    公开(公告)号：US5444394A

    公开(公告)日：1995-08-22

    申请号：US88973

    申请日：1993-07-08

    申请人： James A. Watson ,  Cameron R. McClintock ,  Hiten S. Randhawa ,  Ken M. Li ,  Bahram Ahanin

    发明人： James A. Watson ,  Cameron R. McClintock ,  Hiten S. Randhawa ,  Ken M. Li ,  Bahram Ahanin

    IPC分类号： H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/1737

    摘要： A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to two stacks of logic array blocks on its sides. The logic array blocks include CMOS look up table based logic modules that consume zero DC power. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes routing flexibility and speed. The combination of low power logic array blocks and high performance global interconnect array allows for increased logic density at lower power consumption compared to prior art programmable logic array devices.

    摘要翻译： 提出了一种可编程逻辑器件，其包括全局互连阵列，其线路经由可编程多路复用器馈送到其侧面上的两个逻辑阵列块堆栈。 逻辑阵列块包括消耗零直流电源的基于CMOS查找表的逻辑模块。 全局互连阵列线以特定的模式馈送到多路复用器，使路由灵活性和速度最大化。 与现有技术的可编程逻辑阵列器件相比，低功率逻辑阵列块和高性能全局互连阵列的组合允许以更低的功耗提高逻辑密度。

    Flexible configuration logic array block for programmable logic devices
    6.
    发明授权
    Flexible configuration logic array block for programmable logic devices 失效
    用于可编程逻辑器件的灵活配置逻辑阵列块

    公开(公告)号：US5341044A

    公开(公告)日：1994-08-23

    申请号：US49064

    申请日：1993-04-19

    申请人： Bahram Ahanin ,  Janusz K. Balicki ,  Khusrow Kiani ,  William Leong ,  Ken-Ming Li ,  Bezhad Nouban

    发明人： Bahram Ahanin ,  Janusz K. Balicki ,  Khusrow Kiani ,  William Leong ,  Ken-Ming Li ,  Bezhad Nouban

    IPC分类号： H03K19/173

    CPC分类号： H03K19/1737

    摘要： A programmable logic device has a number of dedicated global control input lines which interface directly with individual building blocks known as logic array blocks. These lines can be used for clocks, presets, clears, or output-enables. Other logic signal lines from the centrally located global interconnect array are selected through an array of multiplexers and then interface with the logic array block. A configuration array of multiplexers in the logic array block selects from among these inputs, generating local control input signals, the final functions of which are decided by further multiplexing at the macrocell level within the logic array block.

    摘要翻译： 可编程逻辑器件具有多个专用的全局控制输入线，其直接与被称为逻辑阵列块的各个构建块直接连接。 这些线可用于时钟，预设，清零或输出使能。 来自中心位置的全局互连阵列的其他逻辑信号线通过多路复用器阵列进行选择，然后与逻辑阵列块进行接口。 逻辑阵列块中的多路复用器的配置阵列从这些输入中选择产生本地控制输入信号，其最终功能通过在逻辑阵列块内的宏单元级进一步复用来确定。

    Methods and apparatus for facilitating scan testing of asynchronous logic circuitry
    7.
    发明授权
    Methods and apparatus for facilitating scan testing of asynchronous logic circuitry 失效
    用于促进异步逻辑电路的扫描测试的方法和装置

    公开(公告)号：US5166604A

    公开(公告)日：1992-11-24

    申请号：US611974

    申请日：1990-11-13

    申请人： Bahram Ahanin ,  Craig S. Lytle ,  Ricky W. Ho

    发明人： Bahram Ahanin ,  Craig S. Lytle ,  Ricky W. Ho

    IPC分类号： G01R31/317 ,  G01R31/3185

    CPC分类号： G01R31/318558 ,  G01R31/31707

    摘要： Scan testing of asynchronous logic circuitry is facilitated by gating off the asynchronous inputs to flip-flops during scan testing. If desired, the asynchronous inputs which are gated off in this manner may themselves terminals or scan registers during testing. Alternatively, the asynchronous inputs which are gated could be tested by selectively enabling the signals at strategic points during scan testing. The number of input terminals required to control the test mode may be reduced by providing registers for storing test control signals applied to normal input terminals at the beginning of a test cycle. Once these test control signals are stored, the normal input terminals are free to return to their normal use.

    摘要翻译： 通过在扫描测试期间门控异步输入到触发器来促进异步逻辑电路的扫描测试。 如果需要，以这种方式门控的异步输入端可能在测试期间本身可以是终端或扫描寄存器。 或者，可以通过在扫描测试期间在战略点上选择性地启用信号来测试门控的异步输入。 通过提供用于存储在测试周期开始时施加到正常输入端的测试控制信号的寄存器，可以减少控制测试模式所需的输入端子的数量。 一旦存储了这些测试控制信号，正常输入端可以自由返回正常使用。

    Programmable logic array integrated circuits
    8.
    发明授权
    Programmable logic array integrated circuits 失效
    可编程逻辑阵列集成电路

    公开(公告)号：US06897679B2

    公开(公告)日：2005-05-24

    申请号：US10356691

    申请日：2003-01-31

    申请人： Richard G. Cliff ,  L. Todd Cope ,  Cameron R. Mc Clintock ,  William Leong ,  James A. Watson ,  Joseph Huang ,  Bahram Ahanin

    发明人： Richard G. Cliff ,  L. Todd Cope ,  Cameron R. Mc Clintock ,  William Leong ,  James A. Watson ,  Joseph Huang ,  Bahram Ahanin

    IPC分类号： G01R31/3185 ,  G11C8/12 ,  H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/17736 ,  G01R31/318516 ,  G11C8/12 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728

    摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (“LABs”). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

    摘要翻译： 可编程逻辑阵列集成电路具有多个可编程逻辑模块，它们被组合在多个逻辑阵列块（“LAB”）中。 LAB以二维阵列布置在电路上。 提供一个导线网络，用于将任何逻辑模块与任何其他逻辑模块相互连接。 此外，相邻或附近的逻辑模块可以彼此连接，用于在逻辑模块之间提供进位链和/或用于将两个或多个模块连接在一起以提供更复杂的逻辑功能而不必利用一般互连的特殊目的 网络。 提供了所谓的快速或通用导体的另一网络，用于在整个电路中分布广泛使用的逻辑信号，例如时钟和清除信号。 多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。