发明授权
- 专利标题: Bi-CMOS output circuit with limited output voltage
- 专利标题(中): 双CMOS输出电路,输出电压有限
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申请号: US688511申请日: 1991-07-30
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公开(公告)号: US5198704A公开(公告)日: 1993-03-30
- 发明人: Yoshinori Nitta , Takeshi Sugoh , Hiroyuki Hara
- 申请人: Yoshinori Nitta , Takeshi Sugoh , Hiroyuki Hara
- 申请人地址: JPX Kanagawa
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JPX Kanagawa
- 优先权: JPX1-259662 19891004
- 主分类号: H03K17/567
- IPC分类号: H03K17/567 ; H03K19/00 ; H03K19/003 ; H03K19/08 ; H03K19/0944
摘要:
In a Bi-CMOS output circuit constituted by combining a bipolar transistor and a CMOS circuit, in an output circuit obtained by connecting current paths of two bipolar transistors in series between a power source and ground, when the bipolar transistor connected to ground is driven by a bipolar transistor, an output current value can be assured when an output voltage is low. However, when the output voltage is high, a large current is supplied to the bipolar transistor to vary a power source voltage. Therefore, the output terminal of the MOS transistor is connected through a resistor to the grounded control signal input terminal of the bipolar transistor. Since the bipolar transistor connected to the ground is driven by a MOS transistor having drivability lower than that of a normal bipolar transistor, when the output voltage is low, a predetermined current can be assured. When the output voltage is high, supply of a large current can be prevented.
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