发明授权
US5204543A Lateral type semiconductor device having a structure for eliminating
turning-on of parasitic MOS transistors formed therein
失效
具有消除其形成的PARASITIC MOS晶体管导通的结构的横向型半导体器件
- 专利标题: Lateral type semiconductor device having a structure for eliminating turning-on of parasitic MOS transistors formed therein
- 专利标题(中): 具有消除其形成的PARASITIC MOS晶体管导通的结构的横向型半导体器件
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申请号: US918117申请日: 1992-07-22
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公开(公告)号: US5204543A公开(公告)日: 1993-04-20
- 发明人: Toshio Hanazawa , Yukinori Fujimura , Takashi Matsumoto
- 申请人: Toshio Hanazawa , Yukinori Fujimura , Takashi Matsumoto
- 申请人地址: JPX Kawasaki JPX Kasugai
- 专利权人: Fujitsu Limited,Fujitsu VSLI Limited
- 当前专利权人: Fujitsu Limited,Fujitsu VSLI Limited
- 当前专利权人地址: JPX Kawasaki JPX Kasugai
- 优先权: JPX1-81918 19900330
- 主分类号: G03G13/28
- IPC分类号: G03G13/28 ; B41C1/10 ; H01L27/082 ; H01L29/735
摘要:
A semiconductor device comprises a substrate of a first conduction type defined by a major surface, a pair of conductive regions of a second conduction type formed in the substrate along the major surface, an intervening region of the first conduction type formed in the substrate between the pair of conductive regions so as to separate the pair of conductive regions from each other, a first insulator film provided on the substrate so as to cover the major surface thereof including the pair of conductive regions and the intervening region located therebetween, a first conductor layer provided so as to extend generally parallel to the major surface of the substrate with a separation from the first insulator film, the first conductor layer crossing a part of the intervening region at a level separated therefrom, a second conductor layer provided on the first insulator film at a level below the first conductor layer so as to cover at least the part of the intervening region which is crossed by the first conductor layer, a second insulator film interposed between the second conductor layer and the first conductor layer, and a circuit for applying a predetermined voltage to the second conductor layer, the predetermined voltage having a magnitude chosen such that turning-on of a parasitic MOS transistor formed in the semiconductor device is eliminated.
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