公开(公告)号：US5204543A

公开(公告)日：1993-04-20

申请号：US918117

申请日：1992-07-22

申请人： Toshio Hanazawa ,  Yukinori Fujimura ,  Takashi Matsumoto

发明人： Toshio Hanazawa ,  Yukinori Fujimura ,  Takashi Matsumoto

IPC分类号： G03G13/28 ,  B41C1/10 ,  H01L27/082 ,  H01L29/735

CPC分类号： H01L27/0821 ,  H01L29/735

摘要： A semiconductor device comprises a substrate of a first conduction type defined by a major surface, a pair of conductive regions of a second conduction type formed in the substrate along the major surface, an intervening region of the first conduction type formed in the substrate between the pair of conductive regions so as to separate the pair of conductive regions from each other, a first insulator film provided on the substrate so as to cover the major surface thereof including the pair of conductive regions and the intervening region located therebetween, a first conductor layer provided so as to extend generally parallel to the major surface of the substrate with a separation from the first insulator film, the first conductor layer crossing a part of the intervening region at a level separated therefrom, a second conductor layer provided on the first insulator film at a level below the first conductor layer so as to cover at least the part of the intervening region which is crossed by the first conductor layer, a second insulator film interposed between the second conductor layer and the first conductor layer, and a circuit for applying a predetermined voltage to the second conductor layer, the predetermined voltage having a magnitude chosen such that turning-on of a parasitic MOS transistor formed in the semiconductor device is eliminated.

摘要翻译： 半导体器件包括由主表面限定的第一导电类型的衬底，沿着主表面形成在衬底中的第二导电类型的一对导电区域，形成在衬底中的第一导电类型的中间区域 一对导电区域，以将一对导电区域彼此分离;第一绝缘膜，设置在基板上以覆盖其主表面，包括一对导电区域和位于其间的中间区域;第一导体层 所述第一导体层与所述第一绝缘体膜分开地大致平行于所述基板的主表面延伸，所述第一导体层以与其分开的水平度与所述中间区域的一部分交叉;第二导体层，设置在所述第一绝缘膜上 在低于第一导体层的水平处，以至少覆盖交错的中间区域的部分 d，由第二导体层和第一导体层之间插入的第二绝缘体膜，以及用于向第二导体层施加预定电压的电路，所述预定电压的大小被选择为使得导通 形成在半导体器件中的寄生MOS晶体管被消除。