发明授权
US5214320A System and method for reducing ground bounce in integrated circuit
output buffers
失效
用于减少集成电路输出缓冲器中的接地反弹的系统和方法
- 专利标题: System and method for reducing ground bounce in integrated circuit output buffers
- 专利标题(中): 用于减少集成电路输出缓冲器中的接地反弹的系统和方法
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申请号: US897729申请日: 1992-06-12
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公开(公告)号: US5214320A公开(公告)日: 1993-05-25
- 发明人: Ho D. Truong
- 申请人: Ho D. Truong
- 申请人地址: CA San Jose
- 专利权人: Smos Systems, Inc.
- 当前专利权人: Smos Systems, Inc.
- 当前专利权人地址: CA San Jose
- 主分类号: H03K17/16
- IPC分类号: H03K17/16 ; H03K17/687 ; H03K19/0175 ; H03K19/0185
摘要:
A system and method for reducing the amount of ground bounce in output buffer circuits. The invention includes a first control circuit to control the amount of time it takes for a pull-up FET to be turned on, and thus the amount of time it takes for an output signal of the output buffer circuit to transition from a low to a high state. The invention also includes a second control circuit to control the amount of time it takes to turn on a pull down FET and thus the amount of time it takes for the output signal of the output buffer circuit to transition from a high to a low state. First and second control circuits each include an additional FET for controlling the amount of current supplied to the pull-up and pull-down FET, respectively. Each additional FET is driven by a voltage reference signal which is above the threshold of the additional FET. Thus, the additional FET is not fully on or off, but introduces a resistance into the control circuit, thus decreasing the amount of current supplied to the pull-up and pull-down FETs. Since the current amount of current provided to the final output FETs is reduced, their turn-on time is slower and thus the switching time of output buffer circuit is increased. As a result, the magnitude of ground bounce introduced by the output buffer circuit according to the present invention is significantly reduced.
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