公开(公告)号：US5214320A

公开(公告)日：1993-05-25

申请号：US897729

申请日：1992-06-12

申请人： Ho D. Truong

发明人： Ho D. Truong

IPC分类号： H03K17/16 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/0185

CPC分类号： H03K17/163

摘要： A system and method for reducing the amount of ground bounce in output buffer circuits. The invention includes a first control circuit to control the amount of time it takes for a pull-up FET to be turned on, and thus the amount of time it takes for an output signal of the output buffer circuit to transition from a low to a high state. The invention also includes a second control circuit to control the amount of time it takes to turn on a pull down FET and thus the amount of time it takes for the output signal of the output buffer circuit to transition from a high to a low state. First and second control circuits each include an additional FET for controlling the amount of current supplied to the pull-up and pull-down FET, respectively. Each additional FET is driven by a voltage reference signal which is above the threshold of the additional FET. Thus, the additional FET is not fully on or off, but introduces a resistance into the control circuit, thus decreasing the amount of current supplied to the pull-up and pull-down FETs. Since the current amount of current provided to the final output FETs is reduced, their turn-on time is slower and thus the switching time of output buffer circuit is increased. As a result, the magnitude of ground bounce introduced by the output buffer circuit according to the present invention is significantly reduced.

摘要翻译： 一种用于减少输出缓冲电路中的接地反弹量的系统和方法。 本发明包括第一控制电路，用于控制上拉FET导通所花费的时间量，并且因此输出缓冲器电路的输出信号从低电平转换到 高州 本发明还包括一个第二控制电路，用于控制开启下拉FET所需的时间量，并因此控制输出缓冲电路的输出信号从高电平转变为低电平状态所需的时间。 第一和第二控制电路各自包括用于分别控制提供给上拉和下拉FET的电流量的附加FET。 每个附加FET由高于附加FET阈值的电压参考信号驱动。 因此，附加的FET没有完全导通或截止，而是向控制电路引入电阻，从而减少了提供给上拉和下拉FET的电流量。 由于提供给最终输出FET的电流的电流量减少，所以其导通时间较慢，因此输出缓冲电路的切换时间增加。 结果，显着降低了根据本发明的输出缓冲电路引入的地面反弹的幅度。

公开(公告)号：US5444405A

公开(公告)日：1995-08-22

申请号：US255910

申请日：1994-06-08

申请人： Ho D. Truong ,  Chong M. Lin

发明人： Ho D. Truong ,  Chong M. Lin

IPC分类号： H03K5/151 ,  H03K3/037

CPC分类号： H03K5/1515 ,  H03K2005/00058

摘要： A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

摘要翻译： 一种使用独特的可编程片上时钟发生器在芯片上生成和优化具有非重叠边沿的时钟信号的方法。 通过调整片上时钟发生器电路中引入的延迟量来避免时钟信号边沿的重叠。 通过使用硬件和/或软件编程对片上时钟发生器进行编程来调整延迟量。 在硬件编程中，通过物理上改变片上时钟发生器中的延迟元件的组成来调整延迟量。 在软件编程中，使用软件命令调整延迟，以控制片内时钟发生器中的延迟元件的操作，或选择延迟信号的路径。

公开(公告)号：US6031982A

公开(公告)日：2000-02-29

申请号：US749861

申请日：1996-11-15

申请人： Ho D. Truong ,  DongWon Park ,  Hyungsuk Yang ,  Seokkyun Jung

发明人： Ho D. Truong ,  DongWon Park ,  Hyungsuk Yang ,  Seokkyun Jung

IPC分类号： H01L27/06 ,  H01L27/118 ,  G06F17/50 ,  H01L27/10

CPC分类号： H01L27/11807

摘要： A group of function cells (e.g., 40), each created from one or more implementations of a fixed basic cell (20), are utilized in designing a layout for at least part of an integrated circuit. Each basic cell implementation contains a plurality of unconnected transistors (Q1-Q10) arranged in a transistor pattern identical to, or a mirror image of, the transistor pattern in each other basic cell implementation. Transistors of a specified polarity type in each basic cell implementation are normally of two or more different current-carrying capabilities. Each function cell has an interconnection network (42-44) for electrically interconnecting transistors in that function cell to perform a specified electronic function. The function cells typically form a cell library from which certain function cells are selected for generating the layout. The present layout technique is particularly applicable to laying out datapath circuitry (90) in an integrated circuit.

摘要翻译： 在设计集成电路的至少一部分的布局时，利用一组由固定基本单元（20）的一个或多个实施方式创建的功能单元（例如40）。 每个基本单元实现包含以彼此相同的基本单元实现中的晶体管图案相同或者与其相反的晶体管图案布置的多个未连接的晶体管（Q1-Q10）。 每个基本单元实现中的特定极性类型的晶体管通常具有两个或多个不同的载流能力。 每个功能单元具有互连网络（42-44），用于将该功能单元中的晶体管电互连以执行指定的电子功能。 功能单元通常形成单元库，从中选择某些功能单元以生成布局。 本布局技术特别适用于在集成电路中布置数据路径电路（90）。

公开(公告)号：US5877636A

公开(公告)日：1999-03-02

申请号：US733885

申请日：1996-10-18

申请人： Ho D. Truong ,  Edward H. Yu ,  Kathy Ying Chen

发明人： Ho D. Truong ,  Edward H. Yu ,  Kathy Ying Chen

IPC分类号： H03K17/62 ,  H03K5/135 ,  H03K5/13 ,  H03K17/00

CPC分类号： H03K5/135

摘要： An apparatus for multiplexing a pair of test clock signals and a pair of system clock signals onto a pair of output clock signals includes a first means for coupling a first test clock signal to a first output clock signal when a test mode control signal is active, for driving the first output clock signal to an inactive clock signal level when the test mode control signal transitions to an inactive state, and for coupling a first system clock signal to the first output clock signal beginning with a first full clock pulse of the first system clock signal which occurs after the test mode control signal transitions to the inactive state. The apparatus further includes a second means for coupling a second test clock signal to a second output clock when the test mode control signal is active, for driving the second output clock to the inactive clock signal level when the test mode control signal transitions to the inactive state, and for coupling a second system clock signal to the second output clock beginning with a first full clock pulse of the second system clock signal which occurs after the first full clock pulse of the first system clock signal. When exiting the test mode the apparatus ensures that both first and second output clock signals are brought (or held) to an inactive clock signal level, and that system operation begins with the first system clock signal.

摘要翻译： 一种用于将一对测试时钟信号和一对系统时钟信号复用到一对输出时钟信号上的装置包括：当测试模式控制信号有效时将第一测试时钟信号耦合到第一输出时钟信号的第一装置， 用于当所述测试模式控制信号转变到非活动状态时将所述第一输出时钟信号驱动到非活动时钟信号电平，并且用于将所述第一系统时钟信号与所述第一系统的第一全时钟脉冲开始的所述第一输出时钟信号耦合 在测试模式控制信号转变到无效状态之后发生的时钟信号。 该装置还包括第二装置，用于当测试模式控制信号有效时将第二测试时钟信号耦合到第二输出时钟，用于当测试模式控制信号转换到非活动状态时将第二输出时钟驱动到非活动时钟信号电平 状态，并且用于将第二系统时钟信号耦合到第二输出时钟，从第一系统时钟信号的第一全时钟脉冲之后出现的第二系统时钟信号的第一全时钟脉冲开始。 当退出测试模式时，装置确保第一和第二输出时钟信号都被带入（或保持）到不活动时钟信号电平，并且系统操作以第一系统时钟信号开始。