发明授权
US5263172A Multiple speed synchronous bus having single clock path for providing
first or second clock speed based upon speed indication signals
失效
具有单个时钟路径的多速同步总线，用于基于速度指示信号提供第一或第二时钟速度
- 专利标题： Multiple speed synchronous bus having single clock path for providing first or second clock speed based upon speed indication signals
- 专利标题（中）： 具有单个时钟路径的多速同步总线，用于基于速度指示信号提供第一或第二时钟速度
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申请号： US509664申请日： 1990-04-16
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公开(公告)号： US5263172A公开(公告)日： 1993-11-16
- 发明人: Howard T. Olnowich
- 申请人： Howard T. Olnowich
- 申请人地址： NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： NY Armonk
- 主分类号： G06F13/00
- IPC分类号： G06F13/00 ; G06F1/06 ; G06F1/08 ; G06F13/42
摘要：
A computer system which includes a synchronous digital, multibit system bus having a clock path, a master speed indicator path and a slave speed indicator path, a bus control circuit which provides first and second clocks to the clock path of the bus, the second clock having a different frequency than the first clock, and a master circuit and a slave circuit connected to the system bus. The master circuit includes master speed indication circuitry which provides a master speed indicator indicating the operating speed of the master circuit to the master speed indicator path. The slave circuit includes slave speed indication circuitry which provides a slave speed indicator indicating the operating speed of the slave circuit to the slave speed indicator path. The bus controller provides the second clock when the master speed indicator and the slave speed indicator indicate that the master circuit and the slave circuit both may function at the different frequency of the second clock.
公开/授权文献
- US5561665A Automatic frequency offset compensation apparatus 公开/授权日：1996-10-01
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