发明授权
US5267214A Shared-sense amplifier control signal generating circuit in dynamic type
semiconductor memory device and operating method therefor
失效
动态型半导体存储器件中的共享感放大器控制信号发生电路及其操作方法
- 专利标题: Shared-sense amplifier control signal generating circuit in dynamic type semiconductor memory device and operating method therefor
- 专利标题(中): 动态型半导体存储器件中的共享感放大器控制信号发生电路及其操作方法
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申请号: US616264申请日: 1990-11-20
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公开(公告)号: US5267214A公开(公告)日: 1993-11-30
- 发明人: Kazuyasu Fujishima , Yoshio Matsuda , Kazutami Arimoto , Tsukasa Ooishi , Masaki Tsukude
- 申请人: Kazuyasu Fujishima , Yoshio Matsuda , Kazutami Arimoto , Tsukasa Ooishi , Masaki Tsukude
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX2-36666 19900216
- 主分类号: G11C11/409
- IPC分类号: G11C11/409 ; G11C11/401 ; G11C11/4076 ; G11C11/4091 ; H01L21/8242 ; H01L27/108 ; G11C11/34
摘要:
A dynamic random access memory amplifier arrangement includes a sense amplifier band shared between two different memory blocks. In this memory, only sense amplifiers related to a selected memory block are activated. The memory comprises a circuit for boosting a control signal voltage to a switching unit for connecting the selected memory block to the sense amplifiers up to a level higher than a power supply voltage Vcc during the activation of the sense amplifiers, and a circuit for separating a memory block paired with the selected memory block from the activated sense amplifiers during the sensing operation. The memory further comprises a circuit for generating a control signal of the power supply voltage Vcc and connecting all the memory blocks to the corresponding sense amplifiers in a stand-by state wherein a row address strobe signal is inactive. With this arrangement, a highly reliable memory consuming less power can be achieved which ensures data writing and/or rewriting at a full Vcc level.
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