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1.发明授权Semiconductor memory device and data transferring structure and method therein 失效半导体存储器件及其数据传输结构及方法
公开(公告)号：US5894440A
公开(公告)日：1999-04-13
申请号：US189276
申请日：1994-01-31
IPC分类号： G11C11/401 , G11C7/06 , G11C7/10 , G11C11/409
CPC分类号： G11C7/06 , G11C7/1006 , G11C7/1039
摘要： Each of divided bit line pairs is selectively connected to a sub-input/output line pair through transfer gates. A register is connected to the sub-input/output line pair. Data is transferred through the sub-input/output line pair between the register and a selected bit line pair. A sense amplifier is connected to each of the bit line pairs. Sense amplifiers are independently driven by separate sense amplifier activating signals. Therefore, even if data is transferred to the selected bit line pair from the register, fluctuations in potential on the bit line pair caused in such a case does not affect a sense amplifier activating signal connected to a non-selected bit line pair. As a result, data stored in the non-selected memory cell is prevented from being destroyed.
摘要翻译： 每个分开的位线对通过传输门选择性地连接到子输入/输出线对。 寄存器连接到子输入/输出线对。 数据通过寄存器和所选位线对之间的子输入/输出线对传输。 读出放大器连接到每个位线对。 感测放大器由独立的读出放大器激活信号驱动。 因此，即使数据从寄存器传送到所选择的位线对，在这种情况下引起的位线对上的电位波动也不影响连接到未选位线对的读出放大器激活信号。 结果，防止存储在未选择的存储单元中的数据被破坏。
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2.发明授权Shared-sense amplifier control signal generating circuit in dynamic type semiconductor memory device and operating method therefor 失效动态型半导体存储器件中的共享感放大器控制信号发生电路及其操作方法
公开(公告)号：US5267214A
公开(公告)日：1993-11-30
申请号：US616264
申请日：1990-11-20
IPC分类号： G11C11/409 , G11C11/401 , G11C11/4076 , G11C11/4091 , H01L21/8242 , H01L27/108 , G11C11/34
CPC分类号： G11C11/4091 , G11C11/4076
摘要： A dynamic random access memory amplifier arrangement includes a sense amplifier band shared between two different memory blocks. In this memory, only sense amplifiers related to a selected memory block are activated. The memory comprises a circuit for boosting a control signal voltage to a switching unit for connecting the selected memory block to the sense amplifiers up to a level higher than a power supply voltage Vcc during the activation of the sense amplifiers, and a circuit for separating a memory block paired with the selected memory block from the activated sense amplifiers during the sensing operation. The memory further comprises a circuit for generating a control signal of the power supply voltage Vcc and connecting all the memory blocks to the corresponding sense amplifiers in a stand-by state wherein a row address strobe signal is inactive. With this arrangement, a highly reliable memory consuming less power can be achieved which ensures data writing and/or rewriting at a full Vcc level.
摘要翻译： 动态随机存取存储器放大器装置包括在两个不同存储块之间共享的读出放大器带。 在该存储器中，只有与所选存储器块相关的读出放大器被激活。 存储器包括用于将控制信号电压升压到开关单元的电路，用于在感测放大器的激活期间将选择的存储块连接到读出放大器，直到高于电源电压Vcc的电平，以及用于分离 存储块在感测操作期间与所激活的读出放大器与选择的存储块配对。 存储器还包括用于产生电源电压Vcc的控制信号的电路，并且在行地址选通信号无效的待机状态下将所有存储块连接到相应的读出放大器。 通过这种布置，可以实现消耗更少功率的高度可靠的存储器，其确保在完全Vcc级别的数据写入和/或重写。
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3.发明授权Dynamic semiconductor memory device of a twisted bit line system having improved reliability of readout 失效扭转位线系统的动态半导体存储器件具有改进的读出可靠性
公开(公告)号：US4977542A
公开(公告)日：1990-12-11
申请号：US400898
申请日：1989-08-30
IPC分类号： G11C11/401 , G11C7/14 , G11C7/18 , G11C8/14
摘要： An arrangement for providing a compensation of capacitance coupling between word lines and bit lines in a memory structure including twisted bit lines. Two dummy word lines maintained at a predetermined potential are formed at a twisted portion of a pair of bit lines. Dummy cells are provided at respective twisted portions of the dummy word lines and the bit lines. A plurality of word lines are formed in a direction intersecting with the bit lines and the word lines are divided into four word line groups according to positions of the twisted portions of the bit line pairs. When an arbitrary word line is selected, a potential of at least one dummy word line corresponding to the word line group to which the selected word line belongs is lowered. Consequently, the rise of the potential of the bit lines caused by the selection of the word line is compensated for by the lowering of the potential of at least one dummy word line, making it possible to decrease errors in reading. Particular cell layer arrangements simplify increase in integration density in the combination of dummy cell compensation with the twisted bit line balancing of capacitance coupling.
摘要翻译： 一种用于在包括扭转位线的存储器结构中提供字线和位线之间的电容耦合补偿的装置。 保持在预定电位的两个虚拟字线形成在一对位线的扭转部分。 在虚拟字线和位线的相应扭转部分设置虚拟单元。 在与位线相交的方向上形成多个字线，并且根据位线对的扭绞部分的位置将字线分成四个字线组。 当选择任意字线时，与所选字线所属的字线组对应的至少一个虚拟字线的电位降低。 因此，通过降低至少一个虚拟字线的电位来补偿由字线的选择引起的位线的电位的上升，使得可以减少读取中的误差。 特殊的单元层布置简化了虚拟单元补偿与电容耦合的扭转位线平衡组合的集成密度的增加。
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公开(公告)号：US5982678A
公开(公告)日：1999-11-09
申请号：US882758
申请日：1997-06-26
IPC分类号： G11C11/413 , G11C7/00 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/82 , H01L27/10
CPC分类号： G11C29/806 , G11C29/781 , G11C8/10
摘要： A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.
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5.发明授权Test signal generator for semiconductor integrated circuit memory and testing method thereof 失效半导体集成电路存储器的测试信号发生器及其测试方法
公开(公告)号：US5022007A
公开(公告)日：1991-06-04
申请号：US506616
申请日：1990-04-10
IPC分类号： G11C11/401 , G11C11/409 , G11C29/00 , G11C29/10 , G11C29/12 , G11C29/34 , G11C29/56
摘要： A test signal generator for a semiconductor integrated circuit memory, wherein when transfer transistors (20, 21, 14, 15) are rendered conductive, a test data cloumn is supplied from an I/O line pair (11, 12) to a column of a register (10) and stored therein. When a transfer (67) is rendered conductive, the test data column written in the register is written in a column of a memory cell (22) in the same pattern and when transfer transistors (16, 17) are rendered conductive, the test data column written in the register is inverted and the, written in the memory cell column, Data in the memory cell column is read out by a word line (13) and amplified by a sense amplifier (5), so that the data and the test data stored in the register are compared by a coincidence detection circuit 8 to detect whether it is coincident or not.
摘要翻译： 一种用于半导体集成电路存储器的测试信号发生器，其中当传输晶体管（20,21,14,15）导通时，测试数据线从I / O线对（11,12）提供到 寄存器（10）并存储在其中。 当传送（67）导通时，写入寄存器的测试数据列以相同的模式写入存储单元（22）的列中，并且当传输晶体管（16,17）导通时，测试数据 写入寄存器的列被反相，并且写入存储单元列中，存储单元列中的数据被字线（13）读出并由读出放大器（5）放大，使得数据和测试 存储在寄存器中的数据由重合检测电路8进行比较，以检测其是否一致。
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公开(公告)号：US6075732A
公开(公告)日：2000-06-13
申请号：US334917
申请日：1999-06-17
IPC分类号： G11C11/413 , G11C7/00 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/82 , H01L27/10
CPC分类号： G11C29/806 , G11C29/781 , G11C8/10
摘要： A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.
摘要翻译： 半导体存储器件包括执行块分割操作的两个存储单元阵列（1a，1b）。 对应于两个存储单元阵列（1a，1b）提供两个备用行（2a，2b）。 备用排解码器（5a，5b）分别用于选择备用行（2a，2b）。 提供了由备用行解码器（5a，5b）共同使用的一个备用行解码器选择信号生成电路（18）。 可以预先设置备用行解码器选择信号生成电路（18），以便当在存储单元阵列（1a，1b）中存在缺陷行时产生备用行解码器选择信号（+ E，ovs SRE + EE） ），并且由行解码器组（4a，4b）选择有缺陷的行。 每个备用行解码器（5a，5b）响应于备用行解码器选择信号（+ E，ovs SRE + EE）和块控制信号被激活。
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公开(公告)号：US5504713A
公开(公告)日：1996-04-02
申请号：US180166
申请日：1994-01-11
CPC分类号： G11C29/806 , G11C29/781
摘要： A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.
摘要翻译： 半导体存储器件包括执行块分割操作的两个存储单元阵列（1a，1b）。 对应于两个存储单元阵列（1a，1b）提供两个备用行（2a，2b）。 备用排解码器（5a，5b）分别用于选择备用行（2a，2b）。 提供了由备用行解码器（5a，5b）共同使用的一个备用行解码器选择信号生成电路（18）。 可以预先设置备用行解码器选择信号生成电路（18），以便当在存储单元阵列（1a，1b）和缺陷行中存在缺陷行时产生备用行解码器选择信号（＆amp; upbar＆S） 由行解码器组（4a，4b）选择。 每个备用行解码器（5a，5b）响应于备用行解码器选择信号（＆amp; S＆amp; S）和块控制信号被激活。
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公开(公告)号：US5289417A
公开(公告)日：1994-02-22
申请号：US958466
申请日：1992-10-08
IPC分类号： G11C29/00
CPC分类号： G11C29/806 , G11C29/781
摘要： A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.
摘要翻译： 半导体存储器件包括执行块分割操作的两个存储单元阵列（1a，1b）。 对应于两个存储单元阵列（1a，1b）提供两个备用行（2a，2b）。 备用排解码器（5a，5b）分别用于选择备用行（2a，2b）。 提供了由备用行解码器（5a，5b）共同使用的一个备用行解码器选择信号生成电路（18）。 可以预先设置备用行解码器选择信号生成电路（18），以便当在存储单元阵列（1a，1b）中存在有缺陷行时产生备用行译码器选择信号（S（OVS）），并且 有缺陷的行由行解码器组（4a，4b）选择。 每个备用行解码器（5a，5b）响应于备用行解码器选择信号（S（OVS））和块控制信号被激活。
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公开(公告)号：US5185744A
公开(公告)日：1993-02-09
申请号：US479568
申请日：1990-02-14
IPC分类号： G11C29/00 , G11C11/401 , G11C29/28 , G11C29/34 , G11C29/40
摘要： A semiconductor memory device comprises a plurality of memory array blocks (B1 to B4). In each of the plurality of memory array blocks (B1 to B4), a line mode test is performed. Results of the line mode tests performed in the memory array blocks (B1 to B4) are outputted to corresponding match lines (ML1 to ML4). A flag compress (30) performs a logic operation on the test results outputted to the plurality of match lines (ML1 to ML4) and outputs the operation results as test results for the plurality of memory array blocks (B1 to B4) to the outside.
摘要翻译： 半导体存储器件包括多个存储器阵列块（B1至B4）。 在多个存储器阵列块（B1〜B4）的每一个中，进行线路模式测试。 在存储器阵列块（B1〜B4）中执行的线路模式测试的结果被输出到对应的匹配线（ML1〜ML4）。 标志压缩（30）对输出到多个匹配线（ML1〜ML4）的测试结果进行逻辑运算，并将作为多个存储器阵列块（B1〜B4）的测试结果的运算结果输出到外部。
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10.发明授权Semiconductor memory device having on-chip test circuit and method for testing the same 失效具有片上测试电路的半导体存储器件及其测试方法
公开(公告)号：US5184327A
公开(公告)日：1993-02-02
申请号：US727218
申请日：1991-07-09
IPC分类号： G11C29/30
CPC分类号： G11C29/30
摘要： In a memory cell array of a semiconductor memory device, a plurality of detection circuits (14, 15, 20) are provided in correspondence with a plurality of columns. An output line (L) is provided in common to the detection circuits (14, 15 20). The output line (L) is provided with plural junction points (n1 to nn) to which detection results from the detection circuits (14, 15 20) are separately applied. Dividing transistors (T1 to Tn) are provided between the junction points (n1 to nn). During testing, the word lines (WL1 to WLn) are selected sequentially. Test results for the memory cells (MC1 to MC4) connected to the selected word line are outputted at the corresponding junction points (n1 to nn), respectively. Simultaneously, a dividing transistor corresponding to the selected word line is rendered non-conductive, the remaining dividing transistors being rendered conductive. As a result, the output line (L) is divided into two parts at a portion of the non-conductive transistor. Detection results outputted to the respective divided parts of the output line (L) are monitored and a portion at which a detection result is changed in each divided part is found out.
摘要翻译： 在半导体存储器件的存储单元阵列中，与多个列对应地提供多个检测电路（14,15,20）。 输出线（L）与检测电路（14,1520）共同设置。 输出线（L）具有分别施加有检测电路（14,15,20）的检测结果的多个连接点（n1〜nn）。 分接晶体管（T1至Tn）设置在连接点（n1至nn）之间。 在测试期间，顺序选择字线（WL1至WLn）。 连接到所选字线的存储单元（MC1至MC4）的测试结果分别在对应的连接点（n1至nn）输出。 同时，与所选字线对应的分割晶体管不导通，剩余的分割晶体管导通。 结果，输出线（L）在非导电晶体管的一部分被分成两部分。 检测输出到输出线（L）的分割部分的检测结果，并且求出检测结果在各分割部分发生变化的部分。
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