发明授权
US5267246A Apparatus and method for simultaneously presenting error interrupt and
error data to a support processor
失效
同时向支持处理器提供错误中断和错误数据的装置和方法
- 专利标题： Apparatus and method for simultaneously presenting error interrupt and error data to a support processor
- 专利标题（中）： 同时向支持处理器提供错误中断和错误数据的装置和方法
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申请号： US213560申请日： 1988-06-30
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公开(公告)号： US5267246A公开(公告)日： 1993-11-30
- 发明人: Kevin C. Huang , John G. Santoni , Gregory S. Still
- 申请人： Kevin C. Huang , John G. Santoni , Gregory S. Still
- 申请人地址： NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： NY Armonk
- 主分类号： G06F11/34
- IPC分类号： G06F11/34 ; G06F9/46 ; G06F9/48 ; G06F11/00 ; G06F11/07 ; G06F11/273 ; G06F11/30
摘要：
Apparatus and method for collecting and analyzing machine check interrupts generated by a central processor complex. Each logic card is scanned to detect the presence of error data generated by logic circuits on the card. A primary maintenance interface card collects the interrupt information identifying the interrupt as to type of interrupt and location of the card generating the interrupt. A system support adapter reports the collected interrupt information over a LAN to a support processor which may thereafter initiate diagnostic operations with the central processor complex.
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