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公开(公告)号：US5039939A
公开(公告)日：1991-08-13
申请号：US291919
申请日：1988-12-29
IPC分类号： G01R31/28 , G01R31/3185 , H01L21/66
CPC分类号： G01R31/31858
摘要： Chip performance is measured using LSSD logic to propagate a signal through the LSSD scan path of the chip. The measurement data is compared to tabular data which is used to classify the AC chip performance. The use of the LSSD scan path provides an accurate overall measurement of an entire chip. The circuitry is internal to the system and does not require external test circuitry. No unique test patterns are required for a given chip design. The chip measurements can be made after installation of the chip in a field operational environment as well as during a manufacturing and testing environment. The chip measurements can be made by local execution of the testing or controlled from a remote location.
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公开(公告)号：US08645640B2
公开(公告)日：2014-02-04
申请号：US13166054
申请日：2011-06-22
申请人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory S. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
发明人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory S. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
IPC分类号： G06F12/00
CPC分类号： G06Q50/10
摘要： An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value.
摘要翻译： 公开了一种用于在具有多个小灯的数据处理系统内提供系统存储器使用限制的装置。 该装置包括系统存储器，存储器访问收集模块，存储器信用计费模块和存储器调节计数器。 存储器访问收集模块从小数点内的第一高速缓冲存储器接收来自第一高速缓冲存储器的第一组信号和来自第二高速缓冲存储器的第二组信号。 存储器信用计费模块根据从小巧的第一和第二高速缓存存储器的第一和第二组信号中提取的高速缓存访问的结果来跟踪每用户虚拟分区上的系统存储器的使用情况。 存储器油门计数器用于提供节气门控制信号，以防止当系统存储器使用量超过预定值时对系统存储器的访问。
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3.发明授权Determining server resources accessible to client nodes using information received at the server via a communications medium 失效使用通过通信介质在服务器接收的信息来确定客户机节点可访问的服务器资源公开(公告)号：US07451219B2
公开(公告)日：2008-11-11
申请号：US10702179
申请日：2003-11-05
IPC分类号： G06F13/00
CPC分类号： G06F21/6218
摘要： Resources of a server node are logically divided into a plurality of sets of resources. At least one set of resources is assigned to one or more client nodes. The association of the at least one set of resources with the one or more client nodes is via a data structure stored at the server node. The data structure is provided by a trusted agent over a communications medium coupling the server node and the one or more client nodes. It includes information that indicates the resources accessible by the client nodes. To access the information, an identifier, also provided by a trusted agent, is employed.
摘要翻译： 服务器节点的资源在逻辑上被划分为多组资源。 至少一组资源被分配给一个或多个客户端节点。 至少一组资源与一个或多个客户端节点的关联是经由存储在服务器节点处的数据结构。 数据结构由可信代理通过耦合服务器节点和一个或多个客户端节点的通信介质提供。 它包括指示客户机节点可访问的资源的信息。 为了访问信息，使用也由可信代理提供的标识符。
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公开(公告)号：US08683160B2
公开(公告)日：2014-03-25
申请号：US13165982
申请日：2011-06-22
IPC分类号： G06F12/00
CPC分类号： G06Q50/10 , G06F12/0897
摘要： An apparatus for providing memory energy accounting within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory throttle counter, and a memory credit accounting module. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet.
摘要翻译： 公开了一种用于在具有多个小灯的数据处理系统内提供存储器能量记帐的装置。 该装置包括系统存储器，存储器访问收集模块，存储器调节计数器和存储器信用计费模块。 存储器访问收集模块从小数点内的第一高速缓冲存储器接收来自第一高速缓冲存储器的第一组信号和来自第二高速缓冲存储器的第二组信号。 存储器信用计费模块根据从小巧的第一和第二高速缓冲存储器的第一和第二组信号提取的高速缓存访问的结果跟踪每个用户的系统存储器的使用情况。
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公开(公告)号：US20120330803A1
公开(公告)日：2012-12-27
申请号：US13166054
申请日：2011-06-22
申请人： MICHAEL S. FLOYD , GUY L. GUTHRIE , KARTHICK RAJAMANI , GREGORY S. STILL , JEFFREY A. STUECHELI , MALCOLM S. WARE
发明人： MICHAEL S. FLOYD , GUY L. GUTHRIE , KARTHICK RAJAMANI , GREGORY S. STILL , JEFFREY A. STUECHELI , MALCOLM S. WARE
CPC分类号： G06Q50/10
摘要： An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value.
摘要翻译： 公开了一种用于在具有多个小灯的数据处理系统内提供系统存储器使用限制的装置。 该装置包括系统存储器，存储器访问收集模块，存储器信用计费模块和存储器调节计数器。 存储器访问收集模块从小数点内的第一高速缓冲存储器接收来自第一高速缓冲存储器的第一组信号和来自第二高速缓冲存储器的第二组信号。 存储器信用计费模块根据从小巧的第一和第二高速缓存存储器的第一和第二组信号中提取的高速缓存访问的结果来跟踪每用户虚拟分区上的系统存储器的使用情况。 存储器油门计数器用于提供节气门控制信号，以防止当系统存储器使用量超过预定值时对系统存储器的访问。
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公开(公告)号：US20120330802A1
公开(公告)日：2012-12-27
申请号：US13165982
申请日：2011-06-22
CPC分类号： G06Q50/10 , G06F12/0897
摘要： An apparatus for providing memory energy accounting within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory throttle counter, and a memory credit accounting module. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet.
摘要翻译： 公开了一种用于在具有多个小灯的数据处理系统内提供存储器能量记帐的装置。 该装置包括系统存储器，存储器访问收集模块，存储器调节计数器和存储器信用计费模块。 存储器访问收集模块从小数点内的第一高速缓冲存储器接收来自第一高速缓冲存储器的第一组信号和来自第二高速缓冲存储器的第二组信号。 存储器信用计费模块根据从小巧的第一和第二高速缓冲存储器的第一和第二组信号提取的高速缓存访问的结果跟踪每个用户的系统存储器的使用情况。
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公开(公告)号：US20120260117A1
公开(公告)日：2012-10-11
申请号：US13079842
申请日：2011-04-05
申请人： Emrah Acar , Pradip Bose , Bishop C. Brock , Alper Buyuktosunoglu , Michael S. Floyd , Maria L. Pesantez , Gregory S. Still
发明人： Emrah Acar , Pradip Bose , Bishop C. Brock , Alper Buyuktosunoglu , Michael S. Floyd , Maria L. Pesantez , Gregory S. Still
IPC分类号： G06F1/28
CPC分类号： G06F1/3243 , Y02D10/152
摘要： A mechanism is provided for automatically tuning power proxy architectures. Based on the set of conditions related to an application being executed on a microprocessor core, a weight factor to use for each activity in a set of activities being monitored for the microprocessor core is identified, thereby forming a set of weight factors. A power usage estimate value is generated using the set of activities and the set of weight factors. A determination is made as to whether the power usage estimate value is greater than a power proxy threshold value identifying a maximum power usage for the microprocessor core. Responsive to the power usage estimate value being greater than the power proxy threshold value, a set of signals is sent to one or more on-chip actuators in the power proxy unit associated with the microprocessor core and a set of operational parameters associated with the component are adjusted.
摘要翻译： 提供了一种自动调整电源代理架构的机制。 基于与在微处理器核心上执行的应用有关的一组条件，识别用于针对微处理器核心的一组活动中的每个活动的权重因子，从而形成一组权重因子。 使用一组活动和一组权重因子生成用电量估计值。 确定功率使用估计值是否大于识别微处理器核的最大功率使用的功率代理阈值。 响应于功率使用估计值大于功率代理阈值，一组信号被发送到与微处理器核心相关联的功率代理单元中的一个或多个片上致动器，以及与该组件相关联的一组操作参数 被调整。
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8.发明授权公开(公告)号：US08930589B2
公开(公告)日：2015-01-06
申请号：US12869535
申请日：2010-08-26
CPC分类号： G06F11/3442 , G06F11/3476 , G06F2201/88 , G06F2201/885
摘要： According to one aspect of the present disclosure a method and technique for monitoring memory access is disclosed. The method includes monitoring access to a memory unit, updating an activity cache associated with an incrementor with access data corresponding to accesses to the memory unit, monitoring a rate of access to the memory unit, adjusting a sample rate of the access data for storage in the memory unit based on the rate of access, and scaling a value of the access data based on the sample rate.
摘要翻译： 根据本公开的一个方面，公开了一种用于监视存储器访问的方法和技术。 该方法包括监视对存储器单元的访问，使用与对存储器单元的访问相对应的访问数据来更新与增量器相关联的活动高速缓存，监视对存储器单元的访问速率，调整访问数据的采样率以便存储 基于访问速率的存储器单元，以及基于采样率来缩放访问数据的值。
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公开(公告)号：US08719607B2
公开(公告)日：2014-05-06
申请号：US13308884
申请日：2011-12-01
CPC分类号： G06F1/3293 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A mechanism for power management of processors using Pstates is provided. In a chiplet of a processor in a data processing system, a request is received to change a Pstate from a current Pstate to a requested Pstate. A determination is made as to whether the requested Pstate is less than or equal to a maximum Pstate. Responsive to the requested Pstate being less than or equal to the maximum Pstate, a frequency associated with the requested Pstate is computed thereby forming a computed frequency. An operating frequency of the chiplet is then adjusted to the computed frequency without involvement from a central power control entity.
摘要翻译： 提供了使用Pstates处理器进行电源管理的机制。 在数据处理系统中的处理器的小灯中，接收到将Pstate从当前Pstate更改为所请求的Pstate的请求。 确定所请求的Pstate是否小于或等于最大Pstate。 响应于所请求的Pstate小于或等于最大Pstate，计算与所请求的Pstate相关联的频率，从而形成计算出的频率。 然后将小灯的工作频率调整到计算出的频率，而不受中央功率控制实体的参与。
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公开(公告)号：US08635483B2
公开(公告)日：2014-01-21
申请号：US13079842
申请日：2011-04-05
申请人： Emrah Acar , Pradip Bose , Bishop C. Brock , Alper Buyuktosunoglu , Michael S. Floyd , Maria L. Pesantez , Gregory S. Still
发明人： Emrah Acar , Pradip Bose , Bishop C. Brock , Alper Buyuktosunoglu , Michael S. Floyd , Maria L. Pesantez , Gregory S. Still
CPC分类号： G06F1/3243 , Y02D10/152
摘要： A mechanism is provided for automatically tuning power proxy architectures. Based on the set of conditions related to an application being executed on a microprocessor core, a weight factor to use for each activity in a set of activities being monitored for the microprocessor core is identified, thereby forming a set of weight factors. A power usage estimate value is generated using the set of activities and the set of weight factors. A determination is made as to whether the power usage estimate value is greater than a power proxy threshold value identifying a maximum power usage for the microprocessor core. Responsive to the power usage estimate value being greater than the power proxy threshold value, a set of signals is sent to one or more on-chip actuators in the power proxy unit associated with the microprocessor core and a set of operational parameters associated with the component are adjusted.
摘要翻译： 提供了一种自动调整电源代理架构的机制。 基于与在微处理器核心上执行的应用有关的条件集合，识别用于针对微处理器核心的一组活动中的每个活动的权重因子，从而形成一组权重因子。 使用一组活动和一组权重因子生成用电量估计值。 确定功率使用估计值是否大于识别微处理器核的最大功率使用的功率代理阈值。 响应于功率使用估计值大于功率代理阈值，一组信号被发送到与微处理器核心相关联的功率代理单元中的一个或多个片上致动器，以及与组件相关联的一组操作参数 被调整。
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