发明授权
- 专利标题: Semiconductor memory device
- 专利标题(中): 半导体存储器件
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申请号: US972913申请日: 1992-11-06
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公开(公告)号: US5289428A公开(公告)日: 1994-02-22
- 发明人: Katsuyuki Sato , Miki Matsumoto , Sadayuki Ohkuma , Masahiro Ogata , Masahiro Yoshida
- 申请人: Katsuyuki Sato , Miki Matsumoto , Sadayuki Ohkuma , Masahiro Ogata , Masahiro Yoshida
- 申请人地址: JPX Tokyo
- 专利权人: Hitachi Ltd., and Hitachi VLSI Engineering Corp.
- 当前专利权人: Hitachi Ltd., and Hitachi VLSI Engineering Corp.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX1-65843 19890320
- 主分类号: G11C29/00
- IPC分类号: G11C29/00 ; G11C7/10 ; G11C7/18 ; G11C8/10 ; G11C11/401 ; G11C29/04 ; G11C13/00
摘要:
A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed. Further features included a redundancy system for relief of defective bits, the use of common bit lines to improve integration density and an improved refreshing arrangement to reduce power consumption during the refresh mode.
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