A DRAM according to the invention is provided with a memory cell array formed by arranging in the row and column directions one-transistor-one-capacitor type memory cells; bit lines, precharged at a prescribed timing, for performing the transfers of write-in/read-out data to and from the memory cells; a sense amplifier including a first transistor, whose drains are connected to the bit lines to bias the substrate to a prescribed potential, and a second transistor whose drains and sources are connected to the sources of the first transistor and a ground potential point, respectively, whose gates receive an activation control signal and whose substrate is biased to the same potential as the first transistor is, for amplifying the signals of said bit lines when activated; an intermediate potential generating circuit for supplying an intermediate potential which is substantially equal to 1/2 of the source potential to the opposite electrodes of said memories and to the bit lines; a power turn-on sensing circuit for generating a sensing signal which takes on an active level after the source potential reaches a prescribed level; and intermediate potential supply control means responsive to the sensing signal for controlling the supply of the intermediate potential to the bit lines.The current sources of said first and second transistors are cut off, power consumption is thereby saved and the occurrence of a latch-up phenomenon suppressed by suspending the supply of the intermediate potential to the bit lines during the period in which, immediately after the power is turned on, the substrate potential rises and the threshold values of the first and second transistors drop to keep these transistors in an ON state.