公开(公告)号：US5319601A

公开(公告)日：1994-06-07

申请号：US958301

申请日：1992-10-08

申请人： Koji Kawata ,  Tadahiko Sugibayashi ,  Takahiro Hara

发明人： Koji Kawata ,  Tadahiko Sugibayashi ,  Takahiro Hara

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/413 ,  H01L27/10 ,  H03K17/00 ,  H03K17/22 ,  G11C13/00 ,  H03K3/01

CPC分类号： G11C5/147 ,  G11C11/4074 ,  H03K17/223 ,  H03K2217/0036

摘要： A power supply circuit for a DRAM has a power-on detection circuit which detects when an external power supply potential reaches a predetermined potential and produces first and second detection signals, and an internal power supply circuit which generates an internal power supply potential. The power supply circuit further has a first intermediate potential generating circuit which generates a first intermediate potential from the external power supply potential and supplies it to an intermediate potential supplying node and, when the first detection signal is produced and the first intermediate potential reaches a predetermined potential, stops the supply of the first intermediate potential to the intermediate potential supplying node and the intermediate potential generating function, and a second intermediate potential generating circuit which generates a second intermediate potential from the internal power supply potential and, when the second detection signal is produced, supplies the second intermediate potential to the supplying node. The first intermediate potential generating circuit has a larger driving capability than that of the second intermediate potential generating circuit. It is made possible to shorten the rising time of the intermediate potential after the power is switched-on and to reduce the overall current consumption.

摘要翻译： 用于DRAM的电源电路具有检测外部电源电位何时达到预定电位并产生第一和第二检测信号的通电检测电路，以及产生内部电源电位的内部电源电路。 电源电路还具有第一中间电位产生电路，其从外部电源电位产生第一中间电位并将其提供给中间电位供给节点，并且当产生第一检测信号并且第一中间电位达到预定的 电位停止向中间电位供给节点和中间电位产生功能提供第一中间电位;以及第二中间电位发生电路，其从内部电源电位产生第二中间电位，当第二检测信号为 产生，向供应节点提供第二中间电位。 第一中间电位产生电路具有比第二中间电位发生电路大的驱动能力。 可以在电源接通之后缩短中间电位的上升时间并减少总体电流消耗。

公开(公告)号：US5337270A

公开(公告)日：1994-08-09

申请号：US935162

申请日：1992-08-26

申请人： Koji Kawata ,  Tadahiko Sugibayashi

发明人： Koji Kawata ,  Tadahiko Sugibayashi

IPC分类号： G11C11/4074 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/24

CPC分类号： G11C11/4074 ,  G11C11/4091 ,  G11C11/4094

摘要： A DRAM according to the invention is provided with a memory cell array formed by arranging in the row and column directions one-transistor-one-capacitor type memory cells; bit lines, precharged at a prescribed timing, for performing the transfers of write-in/read-out data to and from the memory cells; a sense amplifier including a first transistor, whose drains are connected to the bit lines to bias the substrate to a prescribed potential, and a second transistor whose drains and sources are connected to the sources of the first transistor and a ground potential point, respectively, whose gates receive an activation control signal and whose substrate is biased to the same potential as the first transistor is, for amplifying the signals of said bit lines when activated; an intermediate potential generating circuit for supplying an intermediate potential which is substantially equal to 1/2 of the source potential to the opposite electrodes of said memories and to the bit lines; a power turn-on sensing circuit for generating a sensing signal which takes on an active level after the source potential reaches a prescribed level; and intermediate potential supply control means responsive to the sensing signal for controlling the supply of the intermediate potential to the bit lines.The current sources of said first and second transistors are cut off, power consumption is thereby saved and the occurrence of a latch-up phenomenon suppressed by suspending the supply of the intermediate potential to the bit lines during the period in which, immediately after the power is turned on, the substrate potential rises and the threshold values of the first and second transistors drop to keep these transistors in an ON state.

摘要翻译： 根据本发明的DRAM具有通过在行和列方向上布置单晶体管 - 单电容器型存储单元而形成的存储单元阵列; 位线，以规定的时间预充电，用于执行向存储器单元传送写入/读出数据; 包括第一晶体管的读出放大器，其漏极连接到位线以将衬底偏置到规定电位;以及第二晶体管，其漏极和源极分别连接到第一晶体管的源极和地电位点， 其门接收激活控制信号，并且其基板被偏置到与第一晶体管相同的电位，用于在激活时放大所述位线的信号; 中间电位产生电路，用于将基本上等于源极电位的1/2的中间电位提供给所述存储器的相对电极和位线; 电源接通感测电路，用于产生在所述电源电位达到规定电平之后呈现有效电平的感测信号; 以及中间电位供应控制装置，用于响应于感测信号，用于控制对位线的中间电位的供应。 所述第一和第二晶体管的电流源被切断，由此节省功率消耗，并且在电源紧接之后的时段期间通过暂停将中间电位供应给位线来抑制锁存现象的发生 导通时，衬底电位升高，并且第一和第二晶体管的阈值下降以保持这些晶体管处于导通状态。

公开(公告)号：US20070245828A1

公开(公告)日：2007-10-25

申请号：US11640169

申请日：2006-12-18

申请人： Takamasa Nakajima ,  Kazuki Tsuda ,  Zenji Sakai ,  Kazuyoshi Ueno ,  Masakazu Shirahoshi ,  Koji Kawata ,  Yoshikado Yamauchi

发明人： Takamasa Nakajima ,  Kazuki Tsuda ,  Zenji Sakai ,  Kazuyoshi Ueno ,  Masakazu Shirahoshi ,  Koji Kawata ,  Yoshikado Yamauchi

IPC分类号： G01H11/00

CPC分类号： G01M7/02 ,  G01M7/022

摘要： Disclosed is a vibration test method for evaluating the vibration resistance of a specimen, comprising a test specification setting step (S10) of determining reference vibration conditions for the specimen based on transport conditions during actual transportation; a reference value attainment step (S20) of calculating an amplitude level and a reference accumulated fatigue value of the specimen under the reference vibration conditions; a test condition determination step (S30) of determining test vibration conditions and a test time based on an allowable amplification factor of the amplitude level and a desired vibration time, so that an accumulated fatigue value which is calculated from the vibration detection value of the specimen satisfies the reference accumulated fatigue value; and a vibration-imparting step (S40) of vibrating the specimen based on the test vibration conditions and the test time. In accordance with the vibration test method, a vibration test that conforms to the actual transportation environment can be readily performed with high accuracy.

摘要翻译： 公开了一种用于评价试样的抗振性的振动试验方法，其特征在于，包括根据实际运送中的运送条件来确定试样的基准振动条件的试验规格设定步骤（S10） 在参考振动条件下计算样本的振幅水平和基准累积疲劳值的基准值达到步骤（S20） 根据振幅水平的允许放大系数和期望的振动时间来确定测试振动条件和测试时间的测试条件确定步骤（S30），从而根据振幅检测值计算的累积疲劳值 试样满足参考累积疲劳值; 以及基于测试振动条件和测试时间使样本振动的振动赋予步骤（S40）。 根据振动试验方法，可以容易地以高精度进行符合实际运输环境的振动试验。