发明授权
US5347177A System for interconnecting VLSI circuits with transmission line
characteristics
失效
用于将VLSI电路与传输线特性相互连接的系统
- 专利标题: System for interconnecting VLSI circuits with transmission line characteristics
- 专利标题(中): 用于将VLSI电路与传输线特性相互连接的系统
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申请号: US4364申请日: 1993-01-14
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公开(公告)号: US5347177A公开(公告)日: 1994-09-13
- 发明人: Robert J. Lipp
- 申请人: Robert J. Lipp
- 专利权人: Lipp Robert J
- 当前专利权人: Lipp Robert J
- 主分类号: H03K19/00
- IPC分类号: H03K19/00 ; H03K19/003 ; H03K19/017 ; H03K19/0185 ; H04L25/02 ; H03K17/16 ; H03K19/0175
摘要:
This invention provides a means to interconnect high performance CMOS VLSI circuits. LTL (a coined descriptor for describing a novel CMOS interface standard) offers improved performance by providing active threshold control of an input buffer to speed signal capture, and by controlling performance limiting characteristics of signal reflection, ground bounce, receiver overdriving and ringing. These performance limiting characteristics are controlled by providing: level-sensitive impedance control of an output driver, distributed active line termination using impedances of input buffers on a transmission line, and balanced loading using closed-loop transmission lines.
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