发明授权
- 专利标题: Nonvolatile semiconductor memory device
- 专利标题(中): 非易失性半导体存储器件
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申请号: US711532申请日: 1991-06-10
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公开(公告)号: US5347490A公开(公告)日: 1994-09-13
- 发明人: Yasushi Terada , Takeshi Nakayama , Shinichi Kobayashi , Yoshikazu Miyawaki , Masanori Hayashikoshi
- 申请人: Yasushi Terada , Takeshi Nakayama , Shinichi Kobayashi , Yoshikazu Miyawaki , Masanori Hayashikoshi
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX2-158361 19900615
- 主分类号: G11C17/00
- IPC分类号: G11C17/00 ; G11C5/14 ; G11C16/02 ; G11C16/16 ; G11C16/30 ; H01L21/8247 ; H01L27/10 ; H01L27/115 ; G11C11/34
摘要:
Disclosed is a flash EEPROM including a voltage lowering circuit therein for lowering an externally applied high voltage serving as a source of an erase pulse to a predetermined voltage in a range in which a tunnel phenomenon sufficiently occurs in memory cells. The voltage lowered by the voltage lowering circuit is converted into a pulse of a small width, and the converted pulse is then applied as an erase pulse to the memory cells. A flash EEPROM including a memory cell array divided into first and second blocks is also disclosed. An erase pulse applying circuit for applying the voltage lowered by the voltage lowering circuit as an erase pulse to the memory cells, and an erase verify circuit for erase verifying are provided for each of the first and second blocks. The erase pulse applying circuit and the erase verify circuit corresponding to the first block and the ones corresponding to the second block are configured to operate independently.
公开/授权文献
- US5839673A Apparatus for grinding material 公开/授权日:1998-11-24