发明授权
US5357462A Electrically erasable and programmable non-volatile semiconductor memory
with automatic write-verify controller
失效
具有自动写入验证控制器的电可擦除和可编程的非易失性半导体存储器
- 专利标题: Electrically erasable and programmable non-volatile semiconductor memory with automatic write-verify controller
- 专利标题(中): 具有自动写入验证控制器的电可擦除和可编程的非易失性半导体存储器
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申请号: US948002申请日: 1992-09-21
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公开(公告)号: US5357462A公开(公告)日: 1994-10-18
- 发明人: Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
- 申请人: Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
- 申请人地址: JPX Kawasaki
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JPX Kawasaki
- 优先权: JPX3-243743 19910924; JPX3-343363 19911225
- 主分类号: G11C16/10
- IPC分类号: G11C16/10 ; G11C16/12 ; G11C16/26 ; G11C16/34 ; G11C16/02
摘要:
A NAND-cell type EEPROM includes an array of memory cells connected to bit lines. Each cell includes one transistor with a floating gate and a control gate electrode, wherein electrons are tunneled to or from the floating gate to write a data thereinto. A sense/latch circuit is connected to the bit lines, and selectively performs a sense operation and a latch operation of the write data. A program controller is provided for writing the data into a selected memory cell in a designated area, and for reading the data written in the selected cell to verify whether or not its resultant threshold voltage falls within an allowable range. If it is insufficient, the data is rewritten thereinto. A rewrite-data setting section is provided for performing a logic operation with respect to a read data from the selected cell and the write data being latched in the sense/latch circuit, and for updating automatically a rewrite data being stored in the sense/latch circuit with respect to every bit line in accordance with the actual write state as being verified. The sense/latch circuit includes a CMOS flip-flop circuit, which acts as a data-latch at the beginning of the verify operation, and serves as a sense amplifier once after it is reset.
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