发明授权
US5358906A Method of making integrated circuit package containing inner leads with
knurled surfaces
失效
制造具有滚花表面的内引线的集成电路封装的方法
- 专利标题: Method of making integrated circuit package containing inner leads with knurled surfaces
- 专利标题(中): 制造具有滚花表面的内引线的集成电路封装的方法
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申请号: US141455申请日: 1993-10-22
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公开(公告)号: US5358906A公开(公告)日: 1994-10-25
- 发明人: Hee G. Lee
- 申请人: Hee G. Lee
- 申请人地址: KRX
- 专利权人: Gold Star Electron Co., Ltd.
- 当前专利权人: Gold Star Electron Co., Ltd.
- 当前专利权人地址: KRX
- 优先权: KRX15863/1991 19910911
- 主分类号: H01L23/28
- IPC分类号: H01L23/28 ; H01L23/495 ; H01L23/50 ; H01L21/60
摘要:
A lead on chip package comprising a semiconductor chip having a plurality of bonding pads and a plurality of minute protrusions formed at both side portions of the upper surface thereof, an insulating film made of a fluoroethylene film having knurled surfaces, and a plurality of inner leads each directly connected to each corresponding bonding pad of the semiconductor chip and provided with knurled surfaces. The formation of minute protrusions is accomplished by using a radio frequency (RF)-sputtering process at a low temperature. The formation of the knurled surfaces at the inner leads can be accomplished by passing the inner leads between rollers each having a knurled outer surface or by coating a nodule or dendrite layer over the surfaces of inner leads by an electro-plating using a high current density. Using the fluoroethylene film, the insulating film can reduce in thickness. By virtue of the knurled surfaces formed at the inner leads and the insulating film, the adhesion can be improved. It is also possible to prevent an occurrence of parasitic capacitance. As a result, there is provided an effect of assisting packages to be laminate.
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