公开(公告)号：US5745655A

公开(公告)日：1998-04-28

申请号：US375473

申请日：1995-01-19

申请人： Ho-sun Chung ,  Ik-soo Lee

发明人： Ho-sun Chung ,  Ik-soo Lee

IPC分类号： G06G7/60 ,  G06F15/18 ,  G06N3/06 ,  G06N3/063 ,  G06N7/08

CPC分类号： G06N3/0635

摘要： A mapping circuit includes a linear circuit for outputting a signal which is linearly changed with respect to its input, a non-linear circuit for outputting a signal which is non-linearly changed with respect to its input, and an adder for summing the output signals of the linear and non-linear circuits and an external input signal. A chaotic neuron circuit using the mapping circuit has a simple structure and more precise chaos characteristics. A chaotic neural network can thus be formed by the serial and/or parallel interconnection of a plurality of chaotic neuron circuits, wherein the weight of each neuron is controlled.

摘要翻译： 映射电路包括用于输出相对于其输入线性改变的信号的线性电路，用于输出相对于其输入非线性改变的信号的非线性电路，以及用于对输出信号求和的加法器 的线性和非线性电路以及外部输入信号。 使用映射电路的混沌神经元电路具有简单的结构和更精确的混沌特性。 因此，可以通过多个混沌神经元电路的串联和/或并联互连形成混沌神经网络，其中每个神经元的权重被控制。

公开(公告)号：US5442209A

公开(公告)日：1995-08-15

申请号：US253215

申请日：1994-06-02

申请人： Ho-sun Chung

发明人： Ho-sun Chung

IPC分类号： G06N3/063 ,  H01L29/78 ,  H01L29/80

CPC分类号： G06N3/063 ,  H01L29/7831

摘要： A synapse MOS transistor has gate electrodes of different lengths, different widths or different lengths and widths, between one source region and one drain region. Thus, when using the synapse MOS transistor to implement a neural network, the chip area can be greatly reduced.

摘要翻译： 突触MOS晶体管具有在一个源极区域和一个漏极区域之间具有不同长度，不同宽度或不同长度和宽度的栅电极。 因此，当使用突触MOS晶体管来实现神经网络时，芯片面积可以大大降低。

公开(公告)号：US5346847A

公开(公告)日：1994-09-13

申请号：US131707

申请日：1993-10-05

申请人： Young K. Jun

发明人： Young K. Jun

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10808 ,  Y10S257/905

摘要： The invention relates to a semiconductor memory device in which a bit line ring which functions as a bit line is formed at the upper and lower stage of the bit line and a storage node is formed to be overlapped in the same direction with said bit line formed perpendicularly to a word line to improve the integration degree.Therefore, a capacitor area can be increased without an increase of an area of the unit cell to improve the integration degree of a semiconductor memory device and the generation of the bent portion of the active region can be avoided to decrease the distortion.

摘要翻译： 本发明涉及一种半导体存储器件，其中在位线的上部和下部形成用作位线的位线环，并且存储节点形成为与形成的所述位线在相同的方向上重叠 垂直于字线提高整合度。 因此，可以增加电容器面积而不增加单位电池的面积，以提高半导体存储器件的集成度，并且可以避免有源区域的弯曲部分的产生以减小失真。

公开(公告)号：US5314298A

公开(公告)日：1994-05-24

申请号：US886830

申请日：1992-05-22

申请人： Youl Kim

发明人： Youl Kim

IPC分类号： H01L21/50 ,  H01L21/00 ,  B65G59/06

CPC分类号： H01L21/67144 ,  H01L2924/0002

摘要： This invention relates to an automatic lead frame feeding device for a TO-220 semiconductor manufacturing apparatus, which automatically feeds lead frames to die bonding and wire bonding processes for manufacturing TO-220 semiconductor packages, and has an object to provide an automatic lead frame feeding device which can load large quantities of lead frames at a time without using a separate magazine for loading them, and then feed automatically them accurately one by one. To this end, the feeding device includes a loading section including a pair of guide members disposed in spaced opposite relation to each other to stack up lead frames therebetween, a transferring section disposed at one side of the loading section for transverse movement to drop one by one the stacked lead frames in the loading section in sequence beginning with the lowermost lead frame, and a feeding section positioned to feed the dropped lead frame in the loading section to a subsequent process.

摘要翻译： 本发明涉及一种用于TO-220半导体制造装置的自动引线框架馈送装置，其自动馈送引线框以进行裸片焊接和用于制造TO-220半导体封装的引线接合工艺，并且目的是提供一种自动引线框架馈电 该装置可以一次加载大量的引线框架，而不使用单独的刀库来加载它们，然后逐个自动进给。 为此，进给装置包括一个装载部分，该装载部分包括一对引导件，该导向件以彼此间隔开的相对关系设置，以在其间堆叠引线架;传送部分，设置在装载部分的一侧，用于横向运动， 一个是装载部分中堆叠的引线框架，从最下面的引线框架开始，以及馈送部分，其定位成将装载部分中的引入引线框架送入后续处理。

公开(公告)号：US5313520A

公开(公告)日：1994-05-17

申请号：US11105

申请日：1993-01-29

申请人： Dae K. Han

发明人： Dae K. Han

IPC分类号： G06F21/22 ,  G06F12/14 ,  G06F12/16 ,  G06F21/02 ,  G06F21/24 ,  G11C11/00 ,  H04L9/00

CPC分类号： G06F12/1466

摘要： A method and a device are provided for protecting data stored in a ROM of a micoprogram control unit. Such data may take the form of a user program. To protect the data, predetermined code data is written into a predetermined address in the ROM. A code address inputted from outside the microprogram control unit is then compared with the predetermined address. If the inputted code address is determined to match the predetermined address, then code data inputted from outside the microprogram control unit is compared with the predetermined code data. Only after both of these comparisons are successfully made is the data in the ROM allowed to be read outside the microprogram control unit.

摘要翻译： 提供了一种用于保护存储在微控制单元的ROM中的数据的方法和装置。 这样的数据可以采取用户程序的形式。 为了保护数据，将预定码数据写入ROM中的预定地址。 然后将从微程序控制单元外部输入的代码地址与预定地址进行比较。 如果确定输入的代码地址与预定地址相匹配，则从微程序控制单元外部输入的代码数据与预定代码数据进行比较。 只有在两次比较成功之后，才允许在微程序控制单元之外读取ROM中的数据。

公开(公告)号：US5245470A

公开(公告)日：1993-09-14

申请号：US844133

申请日：1992-03-02

申请人： Eun S. Keum

发明人： Eun S. Keum

IPC分类号： G03F1/68 ,  G03F1/76 ,  G03F7/20 ,  G03F9/00 ,  H01L21/027 ,  H01L21/30

CPC分类号： G03F9/7065 ,  G03F1/38 ,  G03F1/50 ,  G03F7/70566

摘要： The present invention relates to a polarizing exposure apparatus using a polarizer for radiating polarized light on a polarizing mask and a method for a polarizing mask, for improved resolution, by using such a polarizing exposure apparatus. The polarizing exposure apparatus using a polarizer comprises a light source for radiating light, a pair of polarizing plates for respectively polarizing light radiated from the light source, a focusing lens for focusing the light polarized through said polarizing plates, a polarizing mask for passing only light of the desired pattern from the polarized light focused through the focusing lens and a reduction projection lens for forming the pattern on a wafer by reducing the light passed through the polarizing mask. The method for fabrication of a polarizing mask comprises a step of depositing a Chromium layer on a quartz substrate, patterning the Cr layer to form a Cr mask, forming a first polarizing film, etching said first polarizing film by using a photosensitive film, forming a second polarizing film to cover said first polarizing film and etching said second polarizing film to be alternatively formed with said first polarizing film. The present invention can improve resolution by using a simple polarizing exposure apparatus and it can fabricate a mask by conventional CAD techniques.

摘要翻译： 本发明涉及通过使用这种偏振曝光装置，使用偏振片对偏振掩模进行偏振光的偏光曝光装置和偏光掩模的方法，以提高分辨率。 使用偏振片的偏光曝光装置包括用于照射光的光源，用于分别偏振从光源照射的光的一对偏振片，用于聚焦偏振透过所述偏振片的光的聚焦透镜，用于仅透过光的偏光掩模 通过聚焦透镜聚焦的偏振光的期望图案和用于通过减少穿过偏振掩模的光在晶片上形成图案的还原投影透镜。 偏振掩模的制造方法包括以下步骤：在石英衬底上沉积铬层，对Cr层进行构图以形成Cr掩模，形成第一偏光膜，通过使用感光膜蚀刻所述第一偏光膜，形成 第二偏振膜，用于覆盖所述第一偏振膜，并且蚀刻所述第二偏振膜以与所述第一偏振膜交替地形成。 本发明可以通过使用简单的偏光曝光装置来提高分辨率，并且可以通过常规CAD技术制造掩模。

公开(公告)号：US5200367A

公开(公告)日：1993-04-06

申请号：US787484

申请日：1991-11-06

申请人： Jun S. Ko

发明人： Jun S. Ko

IPC分类号： H01L21/50 ,  H01L21/56 ,  H01L23/057 ,  H01L23/08

CPC分类号： H01L21/565 ,  H01L21/50 ,  H01L23/057 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/181 ,  Y10T29/49121

摘要： A method for assembling multilayer packages of semi-conductor elements comprising double molding of the multilayer structure. The method comprises the steps of primarily molding inner leads of a lead frame, secondarily molding the inner leads to form a desired package, and performing in turn die bonding, wire bonding, trimming and forming processes. The double molding process is performed by using an inexpensive molding compound, thereby obtaining packages having a structure equivalent to that of expensive ceramic packages. Accordingly, the manufacture cost of packages is inexpensive and the assembling process is simplified.

摘要翻译： 一种用于组装半导体元件的多层封装的方法，包括多层结构的双重成型。 该方法包括以下步骤：主要模制引线框架的内引线，二次模制内引线以形成所需的封装，并进行裸焊，引线接合，修整和成形工艺。 通过使用便宜的成型化合物进行双重成型，得到具有与昂贵的陶瓷包装相当的结构的包装。 因此，包装的制造成本便宜，并且组装过程简化。

公开(公告)号：US5428298A

公开(公告)日：1995-06-27

申请号：US272106

申请日：1994-07-07

申请人： Jun S. Ko

发明人： Jun S. Ko

IPC分类号： G01R1/073 ,  G01R1/067 ,  G01R31/26 ,  G01R31/28 ,  H01L21/66 ,  G01R1/04

CPC分类号： G01R1/06738 ,  G01R31/2863

摘要： A tester applicable to semiconduction chips having a plurality of pins. The tester comprises a TAB tape having an adhesive surface and a plurality of connecting wires attached to the adhesive surface of the TAB tape and connected to a test card. At a probe region of the tester, probe tips are disposed which come into contact with pads of the semiconductor chip to be tested, upon testing. Each probe tip is made of a palladium layer having a serrated edge grown to shape over a nickel film on a portion of each connecting wire, which portion is disposed at the probe region. The tester can test a semiconductor chip having a plurality of pins and carry out simultaneous probings of a semiconductor chip having the number of pins enabling a TAB chip bonding. Both a functional test and a burn-in test may be carried out with a single test system. Since the tester has many sharp probe tips made of dendritic-grown palladium, it can provide an improvement in proving effect. The sharp probe chips also eliminate a non-contact problem.

摘要翻译： 适用于具有多个引脚的半导体芯片的测试器。 测试仪包括具有粘合剂表面的TAB带和附接到TAB带的粘合剂表面并连接到测试卡的多个连接线。 在测试器的探针区域，设置探针尖端，其在测试时与要测试的半导体芯片的焊盘接触。 每个探针尖端由具有锯齿状边缘的钯层制成，其形成在每个连接线的一部分上的镍膜上形成，该部分设置在探针区域处。 测试器可以测试具有多个引脚的半导体芯片，并且执行具有能够进行TAB芯片接合的引脚数量的半导体芯片的同时探测。 功能测试和老化测试都可以使用单个测试系统进行。 由于测试仪具有由树枝状生长的钯制成的许多尖锐的探针尖端，因此可以提供证明效果。 尖锐的探针芯片也消除了非接触问题。

公开(公告)号：US5358906A

公开(公告)日：1994-10-25

申请号：US141455

申请日：1993-10-22

申请人： Hee G. Lee

发明人： Hee G. Lee

IPC分类号： H01L23/28 ,  H01L23/495 ,  H01L23/50 ,  H01L21/60

CPC分类号： H01L23/4951 ,  H01L23/49524 ,  H01L23/49548 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181

摘要： A lead on chip package comprising a semiconductor chip having a plurality of bonding pads and a plurality of minute protrusions formed at both side portions of the upper surface thereof, an insulating film made of a fluoroethylene film having knurled surfaces, and a plurality of inner leads each directly connected to each corresponding bonding pad of the semiconductor chip and provided with knurled surfaces. The formation of minute protrusions is accomplished by using a radio frequency (RF)-sputtering process at a low temperature. The formation of the knurled surfaces at the inner leads can be accomplished by passing the inner leads between rollers each having a knurled outer surface or by coating a nodule or dendrite layer over the surfaces of inner leads by an electro-plating using a high current density. Using the fluoroethylene film, the insulating film can reduce in thickness. By virtue of the knurled surfaces formed at the inner leads and the insulating film, the adhesion can be improved. It is also possible to prevent an occurrence of parasitic capacitance. As a result, there is provided an effect of assisting packages to be laminate.

摘要翻译： 一种芯片封装，包括具有多个接合焊盘的半导体芯片和形成在其上表面的两侧部分的多个微小突起，由具有滚花表面的氟乙烯膜制成的绝缘膜，以及多个内引线 每个直接连接到半导体芯片的每个对应的焊盘并且具有滚花表面。 通过在低温下使用射频（RF）溅射工艺来实现微小突起的形成。 在内引线处形成滚花表面可以通过使内引线在每个具有滚花外表面的辊之间通过使用高电流密度的电镀在内引线的表面上涂覆结核或枝晶层来实现 。 使用氟乙烯膜，绝缘膜的厚度可以减小。 通过形成在内引线和绝缘膜上的滚花表面，可以提高粘合性。 也可以防止寄生电容的发生。 结果，提供了帮助包装件被层压的效果。

公开(公告)号：US5219780A

公开(公告)日：1993-06-15

申请号：US849916

申请日：1992-03-12

申请人： Young K. Jun

发明人： Young K. Jun

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10817

摘要： The present invention relates to a method for fabricating a semiconductor memory cell consisting of a switching transistor and a capacitor wherein a polysilicon pad and a polysilicon storage node are simultaneously patterned with a self-alignment method without a mask.Accordingly, the present invention has the following advantages: First, the overlay accuracy can be improved by patterning a polysilicon pad and a polysilicon storage node with a self-alignment method. Second, the fabrication process can be simpler than the prior fabrication process for the semiconductor memory cell of a noble stacked capacitor cell structure. Third, the storage capacitance of a capacitor can be increased.

摘要翻译： 本发明涉及一种由开关晶体管和电容器组成的半导体存储单元的制造方法，其中多晶硅焊盘和多晶硅存储节点同时用无取向掩模的自对准方法构图。 因此，本发明具有以下优点：首先，通过以自对准方法构图多晶硅焊盘和多晶硅存储节点，可以提高覆盖精度。 第二，制造工艺可以比先前的贵金属叠层电容器单元结构的半导体存储单元的制造工艺简单。 第三，可以增加电容器的存储电容。