发明授权
- 专利标题: Column selector circuit for shared column CMOS EPROM
- 专利标题(中): 用于共享列CMOS EPROM的列选择器电路
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申请号: US847114申请日: 1992-03-06
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公开(公告)号: US5359555A公开(公告)日: 1994-10-25
- 发明人: Robert M. Salter, III
- 申请人: Robert M. Salter, III
- 申请人地址: CA Santa Clara
- 专利权人: National Semiconductor Corporation
- 当前专利权人: National Semiconductor Corporation
- 当前专利权人地址: CA Santa Clara
- 主分类号: G11C17/00
- IPC分类号: G11C17/00 ; G11C16/02 ; G11C16/04 ; G11C16/10 ; H01L21/8247 ; H01L27/115 ; G11C11/34
摘要:
A CMOS memory is disclosed which employs a column selector circuit that prevents write disturb in shared column EPROMs. When a selected memory transistor is programmed, disturb is prevented by selecting all columns on the source side of the selected memory transistor to be tied to the source programming voltage, and selecting all columns on the drain side of the selected memory transistor to be tied to the drain programming voltage. By reducing voltage differentials across non-selected memory transistors, write disturb is prevented. This may be implemented by employing shorting devices between all adjacent columns. When a memory transistor is selected, all the shorting devices except the one between the source and drain columns of the selected memory cell are enabled. This may be further improved to minimize the number of required select lines by employing a shorting device comprising transistors controlled by the normal select lines.
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