The switching element allows building up of ATM exchanges capable of processing cell flows at bit rates higher than 700 Mbit/s. It uses an architecture with output queues, implemented through a unique shared memory, suitably controlled in order to obtain spatial cell switching towards the outputs. ATM cells are converted into a highly parallel format by a structure named rotation memory, where through the cells are then transferred into the master memory. The rotation memory is used also for the inverse operations of format restoration towards the output. The element control circuit is entrusted with the generation of writing and reading addresses of the master memory, in order to carry out the switching proper.