-
公开(公告)号：US5369635A
公开(公告)日：1994-11-29
申请号：US027335
申请日：1993-03-08
IPC分类号： H04L12/54 , H04L12/70 , H04L12/933 , H04Q11/04 , H04L12/56
CPC分类号： H04Q11/0478 , H04L12/5601 , H04L49/108 , H04L49/1553 , H04L2012/5681
摘要： The switching element allows building up of ATM exchanges capable of processing cell flows at bit rates higher than 700 Mbit/s. It uses an architecture with output queues, implemented through a unique shared memory, suitably controlled in order to obtain spatial cell switching towards the outputs. ATM cells are converted into a highly parallel format by a structure named rotation memory, where through the cells are then transferred into the master memory. The rotation memory is used also for the inverse operations of format restoration towards the output. The element control circuit is entrusted with the generation of writing and reading addresses of the master memory, in order to carry out the switching proper.
摘要翻译： 开关元件允许建立能够以高于700Mbit / s的比特率处理小区流的ATM交换机。 它使用具有输出队列的架构，通过独特的共享存储器实现，被适当地控制，以便获得朝向输出的空间单元切换。 ATM单元被称为旋转存储器的结构转换成高度并行的格式，其中通过单元然后被转移到主存储器中。 旋转存储器也用于对输出进行格式恢复的反向操作。 元件控制电路委托生成主存储器的写入和读取地址，以便适当地进行切换。
-
2.发明申请METHOD AND ARRANGEMENT FOR SECURE USER AUTHENTICATION BASED ON A BIOMETRIC DATA DETECTION DEVICE 有权基于生物量数据检测装置的用户认证安全的方法和装置公开(公告)号：US20100049987A1
公开(公告)日：2010-02-25
申请号：US12448309
申请日：2006-12-19
CPC分类号： H04L63/0853 , G06F21/32 , G06F21/34 , G06F21/42 , G06F2221/2107 , H04L63/0861 , H04W12/02 , H04W12/04 , H04W12/06
摘要： An arrangement for secure user authentication includes a computer or telecommunication terminal with a smartcard and a device. The smartcard is adapted to securely store biometric information relating to at least one user and the device is adapted to detect biometric data of users. The smartcard and the device include a radio interface for communicating together and a module for exchanging biometric information between each other. In this way, tampering of the transferred biometric information is difficult. In order to increase the security, one or more of the following measures may be used: a secure communication channel between the device and the smartcard, a direct (preferably short range) communication channel between the device and the smartcard and encryption and decryption of biometric information transferred between the device and the smartcard.
摘要翻译： 用于安全用户认证的安排包括具有智能卡和设备的计算机或电信终端。 智能卡适于安全地存储与至少一个用户有关的生物特征信息，并且该设备适于检测用户的生物特征数据。 智能卡和设备包括用于一起通信的无线电接口和用于彼此之间交换生物信息的模块。 以这种方式，转移的生物特征信息的篡改是困难的。 为了提高安全性，可以使用以下措施之一：设备与智能卡之间的安全通信通道，设备与智能卡之间的直接（优选短距离）通信通道以及生物识别的加密和解密 在设备和智能卡之间传输的信息。
-
3.发明授权Method of expanding the capacity of switching elements, and switching stage obtained by the method 失效扩展开关元件容量的方法以及通过该方法获得的开关级
公开(公告)号：US5946314A
公开(公告)日：1999-08-31
申请号：US729006
申请日：1996-10-10
申请人： Luigi Licciardi , Luciano Pilati , Maura Turolla
发明人： Luigi Licciardi , Luciano Pilati , Maura Turolla
CPC分类号： H04L12/5601 , H04L49/1561 , H04L49/256 , H04L49/455
摘要： The capacity of switching elements, for instance 8.times.8 elements, is expanded, to originate single-stage elements with greater capacity (16.times.16 or 32.times.32), by arranging an even plurality of such elements in an output substage and by placing upstream of the output substage at least a first input substage comprising a corresponding even plurality of the switching elements. The even and, respectively, the odd outputs of the elements of the input substage are connected in an orderly manner to the inputs of the switching elements of the output substage. A routing management logic to obtain single-stage elements is also provided within each individual switching element.
摘要翻译： 扩展开关元件（例如8×8元件）的容量，通过在输出电路中布置偶数个这样的元件并将输出电路的上游放置在位置上，从而产生具有更大容量（16x16或32x32）的单级元件 至少包括相应的偶数个所述开关元件的第一输入分段。 输入子站的元素的奇数和奇数输出的均匀和均匀的顺序连接到输出子级的开关元件的输入端。 在每个单独的开关元件内还提供用于获得单级元件的路由管理逻辑。
-
4.发明授权Method and arrangement for secure user authentication based on a biometric data detection device 有权基于生物特征数据检测装置的安全用户认证的方法和装置公开(公告)号：US08955083B2
公开(公告)日：2015-02-10
申请号：US12448309
申请日：2006-12-19
CPC分类号： H04L63/0853 , G06F21/32 , G06F21/34 , G06F21/42 , G06F2221/2107 , H04L63/0861 , H04W12/02 , H04W12/04 , H04W12/06
摘要： An arrangement for secure user authentication includes a computer or telecommunication terminal with a smartcard and a device. The smartcard is adapted to securely store biometric information relating to at least one user and the device is adapted to detect biometric data of users. The smartcard and the device include a radio interface for communicating together and a module for exchanging biometric information between each other. In this way, tampering of the transferred biometric information is difficult. In order to increase the security, one or more of the following measures may be used: a secure communication channel between the device and the smartcard, a direct (preferably short range) communication channel between the device and the smartcard and encryption and decryption of biometric information transferred between the device and the smartcard.
摘要翻译： 用于安全用户认证的安排包括具有智能卡和设备的计算机或电信终端。 智能卡适于安全地存储与至少一个用户有关的生物特征信息，并且该设备适于检测用户的生物特征数据。 智能卡和设备包括用于一起通信的无线电接口和用于彼此之间交换生物信息的模块。 以这种方式，转移的生物特征信息的篡改是困难的。 为了提高安全性，可以使用以下措施中的一个或多个：设备与智能卡之间的安全通信信道，设备与智能卡之间的直接（优选短距离）通信信道以及生物特征的加密和解密 在设备和智能卡之间传输的信息。
-
5.发明授权Integrated processing unit, particularly for connected speech recognition systems 失效综合处理单元，特别是连接语音识别系统
公开(公告)号：US4907278A
公开(公告)日：1990-03-06
申请号：US211812
申请日：1988-06-27
申请人： Riccardo Cecinati , Alberto Ciaramella , Luigi Licciardi , Maurizio Paolini , Robert Tasso , Giovanni Venuti
发明人： Riccardo Cecinati , Alberto Ciaramella , Luigi Licciardi , Maurizio Paolini , Robert Tasso , Giovanni Venuti
IPC分类号： C07D209/54 , A61K31/415 , A61K31/4184 , A61K31/557 , A61P1/04 , C07C27/00 , C07C29/143 , C07C35/06 , C07C45/00 , C07C47/192 , C07C51/00 , C07C59/11 , C07C59/353 , C07C67/00 , C07C69/67 , C07C69/675 , C07C69/716 , C07C209/00 , C07C209/26 , C07C213/00 , C07C227/00 , C07C227/08 , C07C239/00 , C07C241/00 , C07C243/20 , C07C247/06 , C07C247/12 , C07C247/14 , C07C253/00 , C07C255/31 , C07D235/02 , G10L15/00 , G10L15/12 , G10L15/14
摘要： This connected-speech recognition system uses a two-level hierarchical system, in which the higher-level (master) processor and one or more lower-level units (slaves) process, respectively, the most probably word sequence within a permitted grammar network, and the likelihood of individual words with the grammar network. The lower-level processing performs dynamic programming involving vector and matrix calculation and comparison, and processing speed is improved by an integrated processing unit which has simultaneous access to the external data memory as well as to a high-speed internal microinstruction ROM. One of the aforementioned units can also provide for performing an additional internal test function. The structure features two internal data buses and internal memories for more commonly used data and addresses, for enabling high-speed microinstruction performance and external memory access. The external memory is divided into tables differing structurally but such as to be accessed in uniform manner by the internal addressing unit.
摘要翻译： 该连接语音识别系统使用两级分层系统，其中较高级（主）处理器和一个或多个较低级单元（从站）分别处理允许的语法网络中最可能的字序列， 以及单词与语法网络的可能性。 下级处理执行涉及向量和矩阵计算和比较的动态规划，并且通过具有同时访问外部数据存储器以及高速内部微指令ROM的集成处理单元改进处理速度。 上述单元之一也可以提供执行额外的内部测试功能。 该结构具有两个内部数据总线和内部存储器，用于更常用的数据和地址，以实现高速微指令性能和外部存储器访问。 外部存储器被分成在结构上不同但是由内部寻址单元以均匀方式访问的表格。
-
公开(公告)号：US4905179A
公开(公告)日：1990-02-27
申请号：US186895
申请日：1988-04-27
CPC分类号： G06F7/5306 , G06F7/503 , G06F2207/3876
摘要： The elementary adder, as far as carry propagation is concerned, has two circuit branches: the first is an inverter (II) followed by a transfer gate (T1, T2) activated when two operands have opposite logic levels, in which case it transfers complemented input carry Cin to the output CoutN; the second consists of a 4-transistor series cirucit, two P-MOS (T3, T4) and two N-MOS (T5, T6) geenrating carry output CoutN complemented when the two operands have equal logic levels.
-
公开(公告)号：US4873659A
公开(公告)日：1989-10-10
申请号：US186897
申请日：1988-04-27
CPC分类号： G06F7/575 , G06F2207/3876 , G06F7/49921
摘要： The arithmetic-logic unit has elementary cells performing logic addition, one for each pair of operand bits, which are particularly optimized as far as carry propogation speed is concerned and are controlled by an auxiliary fast logic allowing their performance to be extended to the other operations. The unit also has a control signal generating circuit, subdivided into a first part (DEC1), near the elementary cell of least significant position, which generates an operation selecting signal for all the cells, and into a second part (DEC2), near the elementary cell of most significant position, which generates control signals for the auxiliary logic of each elementary cell.
-
-
-
-
-
-
搜索结果
7 条记录 (耗时 0.036 秒)
