A plurality of word lines extend linearly and parallel to each other. A reference word line is positioned to divide the word lines into two groups of word lines. A plurality of bit lines are folded on the reference word line symmetrically with respect to the reference word line and spaced at intervals from each other. Each of memory elements comprises a capacitive element and a switching transistor having a source connected to the capacitive element, a drain connected to one of the bit lines, and a gate connected to one of the word lines. The memory elements are disposed in a matrix such that they are spaced across and along the word lines and paired memory elements whose switching transistors have drains connected to the same bit line are positioned symmetrically with respect to the reference word line.