发明授权
US5392253A Nonvolatile semiconductor memory device having row decoder supplying a
negative potential to word lines during erase mode
失效
具有在擦除模式期间向字线提供负电位的行解码器的非易失性半导体存储器件
- 专利标题： Nonvolatile semiconductor memory device having row decoder supplying a negative potential to word lines during erase mode
- 专利标题（中）： 具有在擦除模式期间向字线提供负电位的行解码器的非易失性半导体存储器件
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申请号： US918027申请日： 1992-07-24
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公开(公告)号： US5392253A公开(公告)日： 1995-02-21
- 发明人: Shigeru Atsumi , Sumio Tanaka
- 申请人： Shigeru Atsumi , Sumio Tanaka
- 申请人地址： JPX Kawasaki
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JPX Kawasaki
- 优先权： JPX3-186439 19910725
- 主分类号： G11C17/00
- IPC分类号： G11C17/00 ; G11C7/00 ; G11C8/00 ; G11C8/08 ; G11C16/06 ; G11C16/08 ; G11C16/14 ; H01L21/8247 ; H01L27/10 ; H01L27/115
摘要：
A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during another modes.
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