发明授权
- 专利标题: Cache system for reducing memory latency times
- 专利标题(中): 缓存系统,用于减少内存延迟时间
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申请号: US945561申请日: 1992-09-16
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公开(公告)号: US5404484A公开(公告)日: 1995-04-04
- 发明人: Michael S. Schlansker , Vinod K. Kathail , Rajiv Gupta
- 申请人: Michael S. Schlansker , Vinod K. Kathail , Rajiv Gupta
- 申请人地址: CA Palo Alto
- 专利权人: Hewlett-Packard Company
- 当前专利权人: Hewlett-Packard Company
- 当前专利权人地址: CA Palo Alto
- 主分类号: G06F9/38
- IPC分类号: G06F9/38 ; G06F12/08 ; G06F12/12
摘要:
The improved cache system reduces the effects of latency times by utilizing a preload instruction inserted by the compiler into the code. The preload instruction is sent sufficiently in advance of the corresponding load instruction to guarantee that the relevant data is in the cache memory when the load instruction is received. In addition, the invention prevents the pollution of the cache with data that will only be used once during the expected lifetime of the data in the cache. This second feature of the invention assures that a large number of references to data that will only be used once does not result in the contents of the cache being replaced with the subsequent need to reload the contents after the data references have been completed.
公开/授权文献
- US6124040A Composite and process for the production thereof 公开/授权日:2000-09-26
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