发明授权
US5406506A Domino adder circuit having MOS transistors in the carry evaluating paths
失效
多路器加法电路在进位评估路径中具有MOS晶体管
- 专利标题: Domino adder circuit having MOS transistors in the carry evaluating paths
- 专利标题(中): 多路器加法电路在进位评估路径中具有MOS晶体管
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申请号: US149606申请日: 1993-11-09
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公开(公告)号: US5406506A公开(公告)日: 1995-04-11
- 发明人: Xu Jiasheng , Wang Yueming
- 申请人: Xu Jiasheng , Wang Yueming
- 申请人地址: TWX Hsin-Chu
- 专利权人: United Microelectronics Corp.
- 当前专利权人: United Microelectronics Corp.
- 当前专利权人地址: TWX Hsin-Chu
- 主分类号: G06F7/50
- IPC分类号: G06F7/50 ; G06F7/501
摘要:
An improved Domino adder circuit has a carry evaluating logic, including a precharge transistor, an evaluation transistor, and three carry evaluating paths connected the precharge and evaluation transistors, and constituted by five N-channel Metal Oxide Silicon "NMOS" transistors which are connected to and controlled by three input signals respectively. The carry evaluating logic has a carry evaluating point positioned at the top of the carry evaluating paths. The improved Domino adder circuit further has a sum evaluating logic, including a precharge transistor, an evaluation transistor, and four sum evaluating paths connected between the precharge and evaluation transistors, and connected to and controlled by the three input signals respectively. The sum evaluating logic has a sum evaluating point at the top of the sum evaluating paths. A carry generating logic is connected to and controlled by the carry evaluating point to generate a carry output signal, and a sum generating logic is connected to and controlled by the sum evaluating point to generate a sum output signal.
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