公开(公告)号：US5406506A

公开(公告)日：1995-04-11

申请号：US149606

申请日：1993-11-09

申请人： Xu Jiasheng ,  Wang Yueming

发明人： Xu Jiasheng ,  Wang Yueming

IPC分类号： G06F7/50 ,  G06F7/501

CPC分类号： G06F7/5016

摘要： An improved Domino adder circuit has a carry evaluating logic, including a precharge transistor, an evaluation transistor, and three carry evaluating paths connected the precharge and evaluation transistors, and constituted by five N-channel Metal Oxide Silicon "NMOS" transistors which are connected to and controlled by three input signals respectively. The carry evaluating logic has a carry evaluating point positioned at the top of the carry evaluating paths. The improved Domino adder circuit further has a sum evaluating logic, including a precharge transistor, an evaluation transistor, and four sum evaluating paths connected between the precharge and evaluation transistors, and connected to and controlled by the three input signals respectively. The sum evaluating logic has a sum evaluating point at the top of the sum evaluating paths. A carry generating logic is connected to and controlled by the carry evaluating point to generate a carry output signal, and a sum generating logic is connected to and controlled by the sum evaluating point to generate a sum output signal.

摘要翻译： 改进的多米诺加法器电路具有进位评估逻辑，包括预充电晶体管，评估晶体管和连接预充电和评估晶体管的三个进位评估路径，并由五个N沟道金属氧化物硅“NMOS”晶体管构成， 并分别由三个输入信号控制。 进位评估逻辑具有位于进位评估路径顶部的进位评估点。 改进的多米诺加莫尔电路还具有一个和评估逻辑，其包括预充电晶体管，评估晶体管和连接在预充电和评估晶体管之间的四个和评估路径，并分别连接到三个输入信号并由其控制。 总和评估逻辑在总和评估路径的顶部具有总和评估点。 进位产生逻辑连接到进位评估点并由进位评估点控制以产生进位输出信号，并且和产生逻辑连接到和评估点并由和评估点控制以产生和输出信号。