发明授权
US5409847A Manufacturing method of CMOS transistor in which heat treatment at
higher temperature is done prior to heat treatment at low temperature
失效
在低温下进行热处理之前，在较高温度下进行热处理的CMOS晶体管的制造方法
- 专利标题： Manufacturing method of CMOS transistor in which heat treatment at higher temperature is done prior to heat treatment at low temperature
- 专利标题（中）： 在低温下进行热处理之前，在较高温度下进行热处理的CMOS晶体管的制造方法
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申请号： US141727申请日： 1993-10-27
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公开(公告)号： US5409847A公开(公告)日： 1995-04-25
- 发明人: Mizuki Segawa , Yoshiaki Kato , Hiroaki Nakaoka , Takashi Nakabayashi , Atsushi Hori , Hiroshi Masuda , Ichiro Matsuo , Akihira Shinohara , Takashi Uehara , Mitsuo Yasuhira
- 申请人： Mizuki Segawa , Yoshiaki Kato , Hiroaki Nakaoka , Takashi Nakabayashi , Atsushi Hori , Hiroshi Masuda , Ichiro Matsuo , Akihira Shinohara , Takashi Uehara , Mitsuo Yasuhira
- 申请人地址： JPX Osaka
- 专利权人： Matsushita Electric Industrial Co., Ltd.
- 当前专利权人： Matsushita Electric Industrial Co., Ltd.
- 当前专利权人地址： JPX Osaka
- 主分类号： H01L21/8238
- IPC分类号： H01L21/8238 ; H01L21/265
摘要：
Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.
公开/授权文献
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