公开(公告)号：USRE41980E1

公开(公告)日：2010-12-07

申请号：US11984551

申请日：2007-11-19

申请人： Toshiki Yabu ,  Mizuki Segawa

发明人： Toshiki Yabu ,  Mizuki Segawa

IPC分类号： H01L29/41

CPC分类号： H01L24/05 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/5222 ,  H01L24/03 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/12044 ,  H01L2924/30105 ,  Y10S257/915 ,  H01L2924/00014

摘要： A plurality of metal wires are formed on an underlying interlayer insulating film. Areas among the metal wires are filled with a buried insulating film of a silicon oxide film with a small dielectric constant (i.e., a first dielectric film), and thus, a parasitic capacitance of the metal wires can be decreased. On the buried insulating film, a passivation film of a silicon nitride film with high moisture absorption resistance (i.e., a second dielectric film) is formed, and thus, a coverage defect can be avoided. A bonding pad is buried in an opening formed in a part of a surface protecting film including the buried insulating film and the passivation film, so as not to expose the buried insulating film within the opening. Thus, moisture absorption through the opening can be prevented. In this manner, the invention provides a semiconductor device which has a small parasitic capacitance in an area with a small pitch between the metal wires and is free from a coverage defect as well as the moisture absorption through the opening for the bonding pad, and a method of manufacturing the semiconductor device.

摘要翻译： 多个金属线形成在下面的层间绝缘膜上。 金属线中的区域填充有介电常数小的氧化硅膜的掩埋绝缘膜（即，第一介电膜），因此可以降低金属线的寄生电容。 在掩埋绝缘膜上形成具有高耐吸湿性（即第二介电膜）的氮化硅膜的钝化膜，因此可以避免覆盖缺陷。 接合焊盘被埋在形成在包括掩埋绝缘膜和钝化膜的表面保护膜的一部分中的开口中，以便不在开口内露出掩埋绝缘膜。 因此，可以防止通过开口的吸湿。 以这种方式，本发明提供了一种半导体器件，其在金属线之间具有小间距的区域中具有小的寄生电容，并且没有覆盖缺陷以及通过用于焊盘的开口的吸湿性，以及 制造半导体器件的方法。

公开(公告)号：US07126174B2

公开(公告)日：2006-10-24

申请号：US10995283

申请日：2004-11-24

申请人： Mizuki Segawa ,  Isao Miyanaga ,  Toshiki Yabu ,  Takashi Nakabayashi ,  Takashi Uehara ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada ,  Michikazu Matsumoto

发明人： Mizuki Segawa ,  Isao Miyanaga ,  Toshiki Yabu ,  Takashi Nakabayashi ,  Takashi Uehara ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada ,  Michikazu Matsumoto

IPC分类号： H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/76224 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

摘要： An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.

摘要翻译： 形成了比硅衬底的有源区域更高级的隔离。 在有源区域上，形成包括栅极氧化膜，栅电极，栅极保护膜，侧壁等的FET。 绝缘膜沉积在基板的整个顶表面上，并且在绝缘膜上形成用于暴露在有源区上延伸的区域，一部分隔离栅极保护膜的抗蚀剂膜。 不需要提供用于避免与形成连接孔的区域的隔离等的干涉的取向余量。 由于隔离比有源区域以逐步方式更高，所以通过在形成连接孔中的过度蚀刻来防止隔离物与有源区域中杂质浓度低的部分接触。 以这种方式，可以改善半导体器件的集成，并且可以降低半导体器件占据的面积，而不会导致半导体器件中的结电阻的劣化和结漏电流的增加。

公开(公告)号：US20060043496A1

公开(公告)日：2006-03-02

申请号：US11153498

申请日：2005-06-16

申请人： Yasuhiro Kunimasa ,  Mizuki Segawa

发明人： Yasuhiro Kunimasa ,  Mizuki Segawa

IPC分类号： H01L29/76

CPC分类号： H01L21/76885 ,  H01L21/76852 ,  H01L21/76855 ,  H01L23/535 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: an active region formed in a substrate and surrounded with an isolation formed in the substrate; a gate electrode formed above the active region and made of a semiconductor material; and an interconnect formed on the isolation and in the same layer as the gate electrode and made of the same material as the gate electrode. Side surfaces of the gate electrode are formed with insulating sidewalls, respectively. Upper surfaces of the gate electrode and the interconnect and side surfaces of at least a portion of the interconnect are formed with silicide layers, respectively.

摘要翻译： 半导体器件包括：有源区，形成在衬底中，并被形成在衬底中的隔离物包围; 形成在有源区上方并由半导体材料制成的栅电极; 以及形成在与栅极电极隔离并在同一层中并且由与栅电极相同的材料制成的互连。 栅电极的侧表面分别形成有绝缘侧壁。 栅电极的上表面和互连的至少一部分的互连和侧表面分别由硅化物层形成。

公开(公告)号：US06593198B2

公开(公告)日：2003-07-15

申请号：US09954219

申请日：2001-09-18

申请人： Mizuki Segawa

发明人： Mizuki Segawa

IPC分类号： H01L21336

CPC分类号： H01L29/4983 ,  H01L21/28247 ,  H01L21/823468

摘要： Gate insulating film, gate electrode made up of lower and upper gate electrodes, and on-gate passivation film are formed in this order on an Si substrate. Then, a sidewall is formed as a stack of an oxynitride sidewall having an L-shaped cross section and a nitride sidewall, so as to surround the gate electrode and on-gate passivation film. Alternatively, only the lower edge of an L-oxide sidewall may be changed into an oxynitride region. Or an oxide or stacked sidewall and a nitride sidewall, covering the oxide or stacked sidewall, may be formed instead of the oxynitride sidewall. In any of these embodiments, the lower edge of the sidewall is not removed during a wet etching process.

公开(公告)号：US06524904B1

公开(公告)日：2003-02-25

申请号：US09551542

申请日：2000-04-18

申请人： Mizuki Segawa ,  Masatoshi Arai ,  Toshiki Yabu ,  Shunsuke Kugo

发明人： Mizuki Segawa ,  Masatoshi Arai ,  Toshiki Yabu ,  Shunsuke Kugo

IPC分类号： H01L218238

CPC分类号： H01L21/823842

摘要： After P+ ions are implanted into a polysilicon film in an nMOSFET region, a heat treatment is performed to diffuse phosphorus down to the lower part of the polysilicon film. The diffusion reduces the concentration of phosphorus in an upper end portion of the polysilicon film and inhibits the upper end edges of a gate electrode from being increased in size during patterning. Then, B+ ions are implanted into the polysilicon film in a pMOSFET region and the polysilicon film is etched into a gate configuration. Since a heat treatment for simultaneously diffusing phosphorus and boron in the polysilicon film is not performed, the entrance of boron from the gate electrode into a semiconductor substrate is inhibited, while the occurrence of side etching during the formation of an n-type polysilicon gate is suppressed.

摘要翻译： 将P +离子注入nMOSFET区域中的多晶硅膜之后，进行热处理以将磷扩散到多晶硅膜的下部。 扩散减少了多晶硅膜的上端部分中的磷的浓度，并且在图案化期间抑制栅电极的上端边缘的尺寸增大。 然后，在pMOSFET区域中将B +离子注入到多晶硅膜中，并且将多晶硅膜蚀刻成栅极配置。 由于不进行同时扩散多晶硅膜中的磷和硼的热处理，可以抑制从栅极引入到半导体衬底中的硼，同时在形成n型多晶硅栅极时发生侧蚀刻是 被压制

公开(公告)号：US5989992A

公开(公告)日：1999-11-23

申请号：US925442

申请日：1997-09-08

申请人： Toshiki Yabu ,  Mizuki Segawa

发明人： Toshiki Yabu ,  Mizuki Segawa

IPC分类号： H01L21/60 ,  H01L21/316 ,  H01L21/318 ,  H01L21/3205 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L21/44

CPC分类号： H01L24/05 ,  H01L23/3192 ,  H01L23/5222 ,  H01L24/03 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L23/3171 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/12044 ,  H01L2924/30105 ,  Y10S257/915

摘要： A plurality of metal wires are formed on an underlying interlayer insulating film. Areas among the metal wires are filled with a buried insulating film of a silicon oxide film with a small dielectric constant (i.e., a first dielectric film), and thus, a parasitic capacitance of the metal wires can be decreased. On the buried insulating film, a passivation film of a silicon nitride film with high moisture absorption resistance (i.e., a second dielectric film) is formed, and thus, a coverage defect can be avoided. A bonding pad is buried in an opening formed in a part of a surface protecting film including the buried insulating film and the passivation film, so as not to expose the buried insulating film within the opening. Thus, moisture absorption through the opening can be prevented. In this manner, the invention provides a semiconductor device which has a small parasitic capacitance in an area with a small pitch between the metal wires and is free from a coverage defect as well as the moisture absorption through the opening for the bonding pad, and a method of manufacturing the semiconductor device.

摘要翻译： 多个金属线形成在下面的层间绝缘膜上。 金属线中的区域填充有介电常数小的氧化硅膜的掩埋绝缘膜（即，第一介电膜），因此可以降低金属线的寄生电容。 在掩埋绝缘膜上形成具有高耐吸湿性（即第二介电膜）的氮化硅膜的钝化膜，因此可以避免覆盖缺陷。 接合焊盘被埋在形成在包括掩埋绝缘膜和钝化膜的表面保护膜的一部分中的开口中，以便不在开口内露出掩埋绝缘膜。 因此，可以防止通过开口的吸湿。 以这种方式，本发明提供了一种半导体器件，其在金属线之间具有小间距的区域中具有小的寄生电容，并且没有覆盖缺陷以及通过用于焊盘的开口的吸湿性，以及 制造半导体器件的方法。

公开(公告)号：US5296388A

公开(公告)日：1994-03-22

申请号：US729490

申请日：1991-07-12

申请人： Shuichi Kameyama ,  Atsushi Hori ,  Hiroshi Shimomura ,  Mizuki Segawa

发明人： Shuichi Kameyama ,  Atsushi Hori ,  Hiroshi Shimomura ,  Mizuki Segawa

IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/285 ,  H01L21/331

CPC分类号： H01L29/66272 ,  H01L21/2022 ,  H01L21/2652 ,  H01L21/28525 ,  Y10S148/011 ,  Y10S148/124 ,  Y10S438/969

摘要： A fabrication method for semiconductor devices connecting a multi-crystal semiconductor thin film and a semiconductor region including a high density of an impurity formed in a single crystal semiconductor substrate. After forming a N-type semiconductor region as the emitter by ion implanting, for instance, as into a P-type semiconductor region as the base, a polysilicon thin film 114 is deposited so as to be implanted with As ions and then heat treated. In this case, an amorphous portion of the N-type semiconductor region and an amorphous silicon thin film in contact therewith are transformed by solid phase epitaxial growth so as to form a single crystal semiconductor region, a single-crystalline silicon thin film, and a polysilicon thin film, thus forming a bipolar element having an emitter.

摘要翻译： 连接多晶半导体薄膜和包含在单晶半导体衬底中形成的高浓度杂质的半导体区域的半导体器件的制造方法。 在通过离子注入形成作为发射极的N型半导体区域之后，例如作为基底的P型半导体区域，沉积多晶硅薄膜114，以便注入As离子，然后进行热处理。 在这种情况下，通过固相外延生长来转变N型半导体区域的非晶部分和与其接触的非晶硅薄膜，从而形成单晶半导体区域，单晶硅薄膜和 多晶硅薄膜，从而形成具有发射极的双极元件。

公开(公告)号：US5254485A

公开(公告)日：1993-10-19

申请号：US760987

申请日：1991-09-17

申请人： Mizuki Segawa ,  Shuichi Kameyama ,  Hiroshi Shimomura ,  Atsushi Hori

发明人： Mizuki Segawa ,  Shuichi Kameyama ,  Hiroshi Shimomura ,  Atsushi Hori

IPC分类号： H01L21/331 ,  H01L21/265 ,  H01L29/70

CPC分类号： H01L29/66272 ,  Y10S148/01

摘要： There is disclosed a method for manufacturing a bipolar semiconductor device in which emitter region and active base region are formed by implanting impurities of first and second conduction types in a first semiconductor region of the first conduction type to be a collector through a non-single crystalline semiconductor thin film, a second semiconductor thin film is formed on the first semiconductor thin film, and an impurity of the first conduction type is introduced in the second semiconductor thin film after patterning the first and second semiconductor thin film so as to form an emitter electrode.

摘要翻译： 公开了一种制造双极型半导体器件的方法，其中通过将第一和第二导电类型的杂质注入第一导电类型的第一半导体区域中作为集电极的非单晶结构形成发射极区域和有源基极区域 在第一半导体薄膜上形成第二半导体薄膜，在对第一和第二半导体薄膜进行图案化之后，将第一导电类型的杂质引入到第二半导体薄膜中，以形成发射极 。

公开(公告)号：US06870230B2

公开(公告)日：2005-03-22

申请号：US10300798

申请日：2002-11-21

申请人： Takayuki Matsuda ,  Mizuki Segawa

发明人： Takayuki Matsuda ,  Mizuki Segawa

IPC分类号： H01L21/3205 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/52 ,  H01L23/522 ,  H01L27/08

CPC分类号： H01L21/76831 ,  H01L21/76229 ,  H01L21/76802 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481

摘要： An inventive semiconductor device includes: a substrate; a plurality of first projections each including at least a gate electrode and formed on the substrate; and a plurality of second projections formed on the substrate. When a contour surface constituted by the uppermost face of the substrate and by side and upper faces of the first and second projections is measured for every partial area per unit area of the substrate, the maximum partial area of the contour surface is 1.6 or less times larger than the minimum partial area of the contour surface.

摘要翻译： 本发明的半导体器件包括：衬底; 多个第一突起，每个至少包括一个栅电极并形成在该基板上; 以及形成在所述基板上的多个第二突起。 当基板的每单位面积的每个部分面积测量由基板的最上面和第一和第二突起的侧面和上表面构成的轮廓表面时，轮廓表面的最大部分面积为1.6倍以下 大于轮廓表面的最小部分面积。

公开(公告)号：US06720226B2

公开(公告)日：2004-04-13

申请号：US10441046

申请日：2003-05-20

申请人： Mizuki Segawa

发明人： Mizuki Segawa

IPC分类号： H01L21336

CPC分类号： H01L29/4983 ,  H01L21/28247 ,  H01L21/823468

摘要： Gate insulating film, gate electrode made up of lower and upper gate electrodes, and on-gate passivation film are formed in this order on an Si substrate. Then, a sidewall is formed as a stack of an oxynitride sidewall having an L-shaped cross section and a nitride sidewall, so as to surround the gate electrode and on-gate passivation film. Alternatively, only the lower edge of an L-oxide sidewall may be changed into an oxynitride region. Or an oxide or stacked sidewall and a nitride sidewall, covering the oxide or stacked sidewall, may be formed instead of the oxynitride sidewall. In any of these embodiments, the lower edge of the sidewall is not removed during a wet etching process.

摘要翻译： 栅极绝缘膜，由下部和上部栅电极构成的栅电极和栅极钝化膜依次形成在Si衬底上。 然后，将侧壁形成为具有L形横截面和氮化物侧壁的氧氮化物侧壁的叠层，以便围绕栅电极和栅极钝化膜。 或者，只有L氧化物侧壁的下边缘可以改变为氧氮化物区域。 或者可以形成覆盖氧化物或层叠侧壁的氧化物或层叠侧壁和氮化物侧壁，而不是氧氮化物侧壁。 在这些实施例中的任何一个中，在湿蚀刻工艺期间，侧壁的下边缘不被去除。