发明授权
- 专利标题: Direct current booster with test circuit
- 专利标题(中): 直流增压器带测试电路
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申请号: US32995申请日: 1993-03-18
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公开(公告)号: US5420505A公开(公告)日: 1995-05-30
- 发明人: Ichiro Kondo
- 申请人: Ichiro Kondo
- 申请人地址: JPX Tokyo
- 专利权人: NEC Corporation
- 当前专利权人: NEC Corporation
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX4-064420 19920323
- 主分类号: G01R31/26
- IPC分类号: G01R31/26 ; G01R31/28 ; G11C16/06 ; G11C17/00 ; G11C29/00 ; G11C29/02 ; G11C29/06 ; H01L21/66 ; H01L27/10 ; H02M3/07 ; G01R31/00
摘要:
A direct current booster device has a booster which includes a plurality of N-channel MOS field-effect transistors (FETs) each having a gate terminal and a drain terminal joined together and connected in series in the same direction from the input side to the output side, and a plurality of capacitors to which two boosting clock signals of an opposite phase are provided, which are generated by a clock driver circuit and supplied alternately in a one-by-one corresponding relationship so that the two different boosting clock signals are inputted to each pair of adjacent gate-drain terminals of the FETs. A test circuit is provided, which has a plurality of N-channel MOS FETs, the source terminals of which are connected individually to the gate terminals of the FETs of the booster. The drain terminals of the MOS FETs of the test circuit are all connected in common to a test voltage supply terminal of the input unit for a testing voltage which is higher than a maximum voltage generated by the booster and applied to the capacitors. The gate terminals of the MOS FETs of the test circuit are all connected in common to a control signal terminal of a switching unit to which a control signal of a voltage up to the test voltage is supplied.
公开/授权文献
- US4755750A Wafer keys for wafer probe alignment 公开/授权日:1988-07-05
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