利索-全球专利检索

  1. 登录
  2. 注册
发明授权
US5422911A Frequency walled phase lock loop 失效
频率壁锁相环

Frequency walled phase lock loop
摘要：
A selective call receiver (100) includes a phase lock loop frequency synthesizer having a programmable output frequency signal (414) responsive to a control current signal (417). The phase lock loop frequency synthesizer includes a programmable gain current multiplier (412), a gain of which is determined by a control word selected such that a loop gain of the synthesizer remains relatively constant over a predetermined operating domain of a programmable output frequency signal (417). The current multiplier generates (412) the control current signal (417) by subtracting a reference current (415) from a limited current (416), thus bounding a range of the control current signal (417) within a maximum value of substantially the reference current (415) and a minimum value of the difference between the reference current (415) and the limited current (416).
摘要（中）：

选择呼叫接收机（100）包括具有响应于控制电流信号（417）的可编程输出频率信号（414）的锁相环频率合成器。 锁相环频率合成器包括可编程增益电流乘法器（412），其增益由所选择的控制字确定，使得合成器的环路增益在可编程输出频率信号的预定操作域上保持相对恒定（ 417）。 电流乘法器通过从受限电流（416）减去参考电流（415）来产生（412）控制电流信号（417），从而将控制电流信号（417）的范围限定在基本上为参考的最大值内 电流（415）和参考电流（415）与受限电流（416）之间的差的最小值。

公开/授权文献
信息查询
Global Dossier Espacenet
0/0