公开(公告)号：US11991265B2

公开(公告)日：2024-05-21

申请号：US17481357

申请日：2021-09-22

申请人： Intel Corporation

发明人： Elan Banin ,  Evgeny Shumaker ,  Ofir Degani ,  Rotem Banin ,  Shahar Gross

IPC分类号： H04L27/22 ,  H03C3/06 ,  H04B1/04 ,  H04L7/033 ,  H04L27/152

CPC分类号： H04L7/0331 ,  H03C3/06 ,  H04L7/0332 ,  H04L27/152 ,  H04L27/22

摘要： A wireless communication device for asymmetrical frequency spreading including a processor configured to receive a frequency band message comprising a maximum difference and a minimum difference, wherein the maximum difference is between a maximum frequency of a sub-band and a signal frequency, and wherein the minimum difference is between the minimum frequency of the sub-band and the signal frequency compare the maximum difference and the minimum difference with each other; and generate a frequency shift based on the comparison.

公开(公告)号：US11206578B2

公开(公告)日：2021-12-21

申请号：US15660203

申请日：2017-07-26

申请人： Samsung Electronics Co., Ltd.

发明人： Anil Agiwal ,  Hyunseok Ryu ,  Peng Xue

IPC分类号： H04W28/16 ,  H04W74/08 ,  H04L5/00 ,  H04W72/12 ,  H04J11/00 ,  H04B7/0426 ,  H04B7/0452 ,  H04L27/152

摘要： A communication method and a system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT) are provided. The system may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The method includes receiving, from a base station, scheduling information for a first uplink packet transmission in a first time slot, determining whether the first uplink packet transmission in the first time slot is restricted based on information corresponding to a second uplink packet transmission in the first time slot of another terminal, and if the first uplink packet transmission in the first time slot is restricted, skipping the first uplink packet transmission in a first time slot.

公开(公告)号：US10911274B2

公开(公告)日：2021-02-02

申请号：US16586418

申请日：2019-09-27

申请人： Intel Corporation

发明人： Kailash Chandrashekar ,  Ashoke Ravi

IPC分类号： H04L27/00 ,  H04L27/10 ,  H04L27/152 ,  H03M1/82 ,  H03M1/68

摘要： Methods, apparatus, systems and articles of manufacture for wideband and fast chirp generation for radar systems are disclosed herein. An example apparatus includes a phase digital-to-analog converter to convert a digital input that specifies at least one of a phase modulation or a frequency modulation into an analog output, and to generate a phase modulated output centered on an intermediate frequency. The example apparatus also includes a frequency multiplier to frequency multiply the phase modulated output centered on the intermediate frequency by a multiplication factor to generate a chirp signal.

公开(公告)号：US20200112465A1

公开(公告)日：2020-04-09

申请号：US16154196

申请日：2018-10-08

申请人： NXP B.V.

发明人： Siamak DELSHADPOUR ,  Xueyang GENG ,  Ahmad YAZDI

IPC分类号： H04L27/152 ,  H03L7/087 ,  H03L7/089 ,  H03L7/099 ,  H03L7/107 ,  H03K5/24

摘要： Various embodiments relate to a PLL based FSK demodulator, the FSK demodulator comprising a PFD configured to receive an input signal, a fully differential auxiliary charge pump configured to receive and amplify the input signal from the PFD, a capacitor configured to filter the input signal from the auxiliary charge pump and a fully differential slicer configured to demodulate the input signal and output recovered data.

公开(公告)号：US20200092148A1

公开(公告)日：2020-03-19

申请号：US16130087

申请日：2018-09-13

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Yogesh DARWHEKAR ,  Pranav KUMAR ,  Arpan THAKKAR ,  Naveen MAHADEV ,  Srikanth MANIAN

IPC分类号： H04L27/00 ,  H04L27/38 ,  H04L27/148 ,  H04L27/152

摘要： A receiver circuit includes a quadrature signal generator to generate an in-phase (I) signal and a quadrature (Q) signal from a local oscillator signal and an IQ phase sense and control circuit to generate a phase adjustment code responsive to a phase error between quadrature signals generated by a plurality of mixers. The receiver circuit also includes a phase corrector to adjust a phase difference between the I and Q signals from the quadrature signal generator to generate corrected I and Q signals to be provided to the plurality of mixers.

公开(公告)号：US10587275B2

公开(公告)日：2020-03-10

申请号：US16214965

申请日：2018-12-10

申请人： Movellus Circuits Incorporated

发明人： Jeffrey Fredenburg ,  Muhammad Faisal

IPC分类号： H03L7/099 ,  H03L7/081 ,  H03L7/08 ,  H04L27/152 ,  H04L27/00

摘要： A locked loop circuit is disclosed. The locked loop circuit includes phase detection circuitry to generate a first error output based on a phase difference between a first reference input and a locked-loop output. Summing circuitry receives the first error output and a second error signal. The second error signal is based on one from a selection of error values. Oscillator/delay circuitry generates the locked-loop output. For a first mode of operation, the second error signal is based on a first selected error value. For a second mode of operation, the second error signal is based on a second selected error value different than the first selected error value.

公开(公告)号：US10516423B2

公开(公告)日：2019-12-24

申请号：US15621214

申请日：2017-06-13

申请人： IMEC VZW ,  VRIJE UNIVERSITEIT BRUSSEL

发明人： Nereo Markulic ,  Jan Craninckx

IPC分类号： H03C3/09 ,  H03C5/00 ,  H04B1/04 ,  H04L7/00 ,  H04B17/11 ,  H04L27/36 ,  H04L7/033 ,  H04L27/04 ,  H04L27/152

摘要： A polar transmitter provided for transmitting a phase/frequency modulated and amplitude modulated transmit signal and a method for generating a transmit signal using a polar transmitter are described. An example polar transmitter comprises a phase locked loop for generating a phase/frequency modulated precursor of the transmit signal. The phase locked loop comprises at its input a phase error detection unit for detecting a phase error of the precursor fed back from the output of the phase locked loop to the phase error detection unit as a feedback signal. The polar transmitter comprises a digital amplitude modulator for amplitude modulation of the precursor, resulting in the transmit signal. The digital amplitude modulator is arranged within the phase locked loop for amplitude modulation of the precursor before being output by the PLL. The phase error detection unit is further provided for detecting the amplitude of the feedback signal.

公开(公告)号：US10469296B1

公开(公告)日：2019-11-05

申请号：US16058958

申请日：2018-08-08

申请人： ANRITSU COMPANY

发明人： Karam Noujeim

IPC分类号： H04L27/152 ,  H04L27/16 ,  H03D3/00 ,  H04L27/227 ,  G01R19/25 ,  G01R31/28 ,  G01R1/24

摘要： An in-phase (I) and quadrature (Q) demodulator includes an input for receiving a signal, a reference frequency source, and a sampler connected with the input. The sampler includes a sampler strobe connected with the reference frequency source, and a non-linear transmission line (NLTL) connected with the sampler strobe. The NLTL receives a strobe signal generated by the sampler strobe and multiplies a frequency of the strobe signal to generate a sampler signal. When the sampler receives a signal from the input, the sampler is configured to generate and output an intermediate frequency (IF) signal using the sampler signal. A splitter of the demodulator separates the IF signal into an in-phase (I) component and a quadrature (Q) component. Mixers receive the I and Q components and generate I and Q output signals shifted 90° in phase.

公开(公告)号：US20190296949A1

公开(公告)日：2019-09-26

申请号：US16354499

申请日：2019-03-15

申请人： JVC KENWOOD Corporation

发明人： Koji HIROSE ,  Toru FUJIMOTO

IPC分类号： H04L27/152 ,  H04L7/00

摘要： A mixer is connected to a signal generator and an antenna and outputs a signal at an intermediate frequency. A PLL demodulator subjects the signal at the intermediate frequency from the mixer to PLL demodulation. An amplifier amplifies a signal from the PLL demodulator. A detector detects an amount of shift occurring in the PLL demodulator. A detector detects a gain of the amplifier. An FSK demodulator subjects a signal from the amplifier to FSK demodulation. An AFC unit detects a frequency offset in the signal from the amplifier and causes the signal generator to make a correction for the frequency offset detected.

公开(公告)号：US10374849B2

公开(公告)日：2019-08-06

申请号：US15503892

申请日：2015-08-11

申请人： Sony Corporation

发明人： Seiji Kobayashi ,  Toshiyuki Hiroi ,  Katsuyuki Tanaka ,  Tamotsu Ikeda ,  Hitoshi Tomiyama ,  Makoto Sato ,  Hiroyuki Mita

IPC分类号： H04L27/00 ,  H04L27/12 ,  H04L27/14 ,  H04L27/20 ,  H04L27/16 ,  H04L27/227 ,  H04L27/152

摘要： The present technology relates to a signal processing apparatus and method which can suppress increase in power consumption.In an aspect of the present technology, control data, which is for controlling frequency modulation to a carrier signal using digital data to be transmitted, and for suppressing a time average of a fluctuation amount of a frequency modulation amount more than a case of controlling the frequency modulation to the carrier signal using the digital data is generated, the frequency modulation is performed to the carrier signal on the basis of the generated control data, and the carrier signal to which the frequency modulation is performed is transmitted as a transmission signal. The present technology can be applied to, for example, a signal processing apparatus, a transmission apparatus, a reception apparatus, a communication apparatus, or an electronic apparatus having a transmission function, a reception function, or a communication function, or a computer which controls these.