发明授权
US5424660A DECL logic gates which operate with a 3.3 volt supply or less 失效
DECL逻辑门,工作电压为3.3伏或以下

DECL logic gates which operate with a 3.3 volt supply or less
摘要:
A differential emitter coupled logic circuit having an output and a compliment of the output, the circuit comprising: a first emitter coupled transistor pair (Q17 and Q18); a second emitter coupled transistor pair (Q19 and Q20); a third emitter coupled transistor pair (Q25 and Q26); a fourth emitter coupled transistor pair (Q33 and Q34); a filch emitter coupled transistor pair (Q37 and Q38); and a sixth emitter coupled transistor pair (Q35 and Q36).
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