发明授权
US5452308A Method for monitoring symmetrical two-wire bus lines and two-wire bus
interfaces and device for carrying out the method
失效
用于监控对称双线总线和双线总线接口的方法以及用于执行该方法的设备
- 专利标题: Method for monitoring symmetrical two-wire bus lines and two-wire bus interfaces and device for carrying out the method
- 专利标题(中): 用于监控对称双线总线和双线总线接口的方法以及用于执行该方法的设备
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申请号: US43487申请日: 1993-04-06
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公开(公告)号: US5452308A公开(公告)日: 1995-09-19
- 发明人: Detlef Kaminski , Thilo Kuhner , Wolfgang Kremer , Bernd Haussler , Max Reeb , Rolf Adomat , Michael Brodersen , Alexander Dorr , Herbert Fiessinger
- 申请人: Detlef Kaminski , Thilo Kuhner , Wolfgang Kremer , Bernd Haussler , Max Reeb , Rolf Adomat , Michael Brodersen , Alexander Dorr , Herbert Fiessinger
- 申请人地址: DEX Stuttgart
- 专利权人: Mercedes-Benz AG
- 当前专利权人: Mercedes-Benz AG
- 当前专利权人地址: DEX Stuttgart
- 优先权: DEX4211579.5 19920407
- 主分类号: H04L12/24
- IPC分类号: H04L12/24 ; H04L12/26 ; G06F11/00
摘要:
A method for monitoring symmetrical two-wire bus lines and two-wire bus interfaces and a device for carrying out the method provides pulse weighting of low to high transitions or high to low transitions of the two wires operated in phase opposition of a two-wire bus line. The pulse chains thus obtained are used for step sequencing. In each case, one multistep shift function which is assigned to the first bus wire, is supplied with a first, constant logic read in state and can be reset to a second logic state in all-step fashion and, for all-step resetting of a similar second multistep shift function assigned to the second bus while, and vice versa, the step last achieved for each multistep shift function characterizing the respective fault state of the other bus wire. The pulse weighting is achieved by differentiation or high-pass filtering or by pulse generation controlled by state transition. For the pulse weighting, the device uses simple RC elements or edge-controlled monostable times, and for the multistep shift functions, two similar shift registers are used which can be loaded serially and clocked and reset in parallel and which can also be realized in one piece as a component of a monolithic semiconductor circuit by the previously mentioned elements. The device has a fault tolerance which can be programmed with respect to the bit width, and in conjunction with a likewise settable input cutoff frequency permits the decentralized local testing of two wire bus-type networks. The device can be made using CMOS technology, in conjunction with a very low space requirement.
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