Invention Grant
- Patent Title: Address decision system having address check system
- Patent Title (中): 具有地址检查系统的地址决策系统
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Application No.: US275306Application Date: 1994-07-15
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Publication No.: US5459743APublication Date: 1995-10-17
- Inventor: Naoki Fukuda , Shuji Yoshimura , Satoshi Kakuma
- Applicant: Naoki Fukuda , Shuji Yoshimura , Satoshi Kakuma
- Applicant Address: JPX Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JPX Kawasaki
- Priority: JPX3-220180 19910830
- Main IPC: H04M11/00
- IPC: H04M11/00 ; H04L12/28 ; H04L12/70 ; H04L12/56
Abstract:
In an address decision system in an ATM exchange, a table memory stores data showing relationships between VPI/VCI values and addresses. A latch circuit latches a VPI/VCI value contained in a cell transferred via a cell highway. A comparator circuit compares the VPI/VCI values stored in the table memory with the VPI/VCI value latched by the latch and generates a comparator output signal showing, in a normal operation, one of the addresses at which the VPI/VCI value from the latch circuit coincides with one of the VPI/VCI values in the table memory. An address decision unit encodes the comparator output signal and generates an encoded signal based on the comparator output signal. A decoder unit decodes the encoded signal and generates a decoded signal. A check unit receives the comparator output signal and the encoded signal and generates an error signal when the comparator output signal and the encoded signal do not match each other.
Public/Granted literature
- US4378894A Tamper-evident closure Public/Granted day:1983-04-05
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